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Motorola MTX Series Programmer's Reference Manual
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Motorola MTX Series Programmer's Reference Manual

Motorola MTX Series Programmer's Reference Manual

Mtxa/pg4
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See also: Detailed Service Manual , Service Manual
MTX Series Motherboard
Programmer's Reference
Guide
MTXA/PG4
January 2001

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Summary of Contents for Motorola MTX Series

  • Page 1 MTX Series Motherboard Programmer’s Reference Guide MTXA/PG4 January 2001...
  • Page 2 IBM Corp. Timekeeper and Zeropower are trademarks of Thompson Components. Motorola and the Motorola symbol are registered trademarks of Motorola, Inc. All other products mentioned in this document are trademarks or registered trademarks of their respective holders.
  • Page 3 The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as the user of the product, should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment.
  • Page 4 Flammability All Motorola PWBs (printed wiring boards) are manufactured with a flammability rating of 94V-0 by UL-recognized manufacturers. EMI Caution This equipment generates, uses and can radiate electromagnetic energy. It may cause or be susceptible to electromagnetic interference (EMI) if not installed and used with adequate EMI protection.
  • Page 5 While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.
  • Page 6 If the documentation contained herein is supplied, directly or indirectly, to the U.S. Government, the following notice shall apply unless otherwise agreed to in writing by Motorola, Inc. Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (b)(3) of the Rights in Technical Data clause at DFARS 252.227-7013 (Nov.

  • Page 7: Table Of Contents

    Contents About This Manual Summary of Changes ....................xix Overview of Contents ....................xx Comments and Suggestions ..................xx Manual Terminology....................xxi Conventions Used in This Manual................xxii CHAPTER 1 Board Description and Memory Maps Introduction........................1-1 Feature Summary .......................1-1 System Block Diagram ....................1-2 Functional Description....................1-3 Overview......................1-3 Programming Model ....................1-5...
  • Page 8 W83C553 PIB Registers .................. 1-23 Primary and Secondary EIDE Ports ..............1-23 PC87308VUL Super I/O Strapping..............1-24 NVRAM/RTC & Watchdog Timer Registers........... 1-24 Module Configuration and Status Registers............. 1-25 CPU Configuration Register ..............1-25 Base Module Feature Register ..............1-26 Base Module Status Register (BMSR)............
  • Page 9 When PPC Devices are Little-Endian ............2-16 Cycles Originating From PCI ..............2-16 Error Handling ....................2-16 PCI/PPC Contention Handling .................2-18 Transaction Ordering ..................2-19 Registers........................2-20 PPC Registers ....................2-21 Vendor ID/Device ID Registers ..............2-22 Revision ID Register .................2-23 General Control-Status/Feature Registers ..........2-23 Prescaler Adjust Register................2-25 PPC Error Enable Register ................2-26 PPC Error Status Register................2-28 PPC Error Address Register ..............2-30...
  • Page 10 Spurious Vector Generation ..............2-49 Interprocessor Interrupts (IPI)..............2-49 8259 Compatibility..................2-50 Raven-Detected Errors ................2-50 Timers ....................... 2-50 Interrupt Delivery Modes ................2-51 Block Diagram Description................2-52 Program Visible Registers................. 2-54 Interrupt Pending Register (IPR) .............. 2-54 Interrupt Selector (IS) ................2-54 Interrupt Request Register (IRR) ..............
  • Page 11 8259 Mode....................2-77 Current Task Priority Level...............2-78 Architectural Notes ...................2-78 CHAPTER 3 Falcon ECC Memory Controller Chip Set Introduction........................3-1 Overview......................3-1 Bit Ordering Convention ..................3-1 Features.......................3-1 Block Diagrams ......................3-2 Functional Description....................3-6 Performance ......................3-6 Four-beat Reads/Writes ................3-6 Single-beat Reads/Writes ................3-7 DRAM Speeds .....................3-7 ROM/Flash Speeds ..................3-11 PowerPC 60x Bus Interface................3-12 Responding to Address Transfers..............3-13...
  • Page 12 DRAM Attributes Register ............... 3-35 DRAM Base Register................3-37 CLK Frequency Register................3-37 ECC Control Register ................3-38 Error Logger Register ................3-41 Error_Address Register ................3-44 Scrub/Refresh Register................3-44 Refresh/Scrub Address Register ............... 3-45 ROM A Base/Size Register............... 3-46 ROM B Base/Size Register ...............
  • Page 13 Raven’s Involvement ..................4-13 PCI Domain ......................4-13 PCI-SCSI ....................4-13 PCI-Ethernet ....................4-13 ROM/Flash Initialization ..................4-14 Determining PHB Type ................4-14 Determining CPU Type ................4-14 APPENDIX A Related Documentation Motorola Computer Group Documents ..............A-1 Manufacturers’ Documents..................A-1 Related Specifications....................A-4 URLs .........................A-5 xiii...
  • Page 14 List of Figures Figure 1-1. MTX Series System Block Diagram ............1-4 Figure 2-1. Raven Block Diagram ................2-3 Figure 2-2. PCI Spread I/O Cycle Mapping ............2-13 Figure 2-3. Big- to Little-Endian Data Swap............2-15 Figure 2-4. Raven MPIC Block Diagram ..............2-53 Figure 3-1. Falcon Pair Used with DRAM in a System ..........3-3 Figure 3-2.
  • Page 15 List of Tables Table 1-1. MTX Series Features Summary..............1-1 Table 1-2. Default Processor Memory Map...............1-5 Table 1-3. CHRP Memory Map Example..............1-6 Table 1-4. Raven MPC Register Values for CHRP Memory Map......1-8 Table 1-5. PREP Memory Map Example..............1-8 Table 1-6. Raven MPC Register Values for PREP Memory Map ......1-9 Table 1-7.
  • Page 16 Table 4-5. Reset Sources and Devices Affected............4-9 Table 4-6. Error Notification and Handling............. 4-10 Table 4-7. ROM/FLASH Bank Default..............4-14 Table A-1. Motorola Computer Group Documents ..........A-1 Table A-2. Manufacturers’ Documents ..............A-2 Table A-3. Related Specifications ................A-4...

  • Page 17: About This Manual

    About This Manual This manual provides programming information for the MTX motherboard, equipped with a PowerPC Series microprocessor. Extensive programming information is provided for several Application-Specific Integrated Circuit (ASIC) devices used on the boards. Reference information is included in Appendix A for the Large Scale Integration (LSI) devices used on the boards and sources for additional information are listed.

  • Page 18: Overview Of Contents

    Overview of Contents Chapter 1, Board Description and Memory Maps, briefly describes the board level hardware features of the MTX series motherboard. Chapter 2, Raven PCI Host Bridge & Multi-Processor Interrupt Controller, describes the architecture and usage of the Raven, a PowerPC to PCI Local Bus Bridge ASIC.

  • Page 19: Manual Terminology

    Manual Terminology Throughout this manual, a convention is used which precedes data and address parameters by a character identifying the numeric format as follows: dollar specifies a hexadecimal character percent specifies a binary number & ampersand specifies a decimal number For example, “12”...

  • Page 20: Conventions Used In This Manual

    A word or single word is 32 bits, numbered 0 through 31, with bit 0 being the least significant. A double word is 64 bits, numbered 0 through 63, with bit 0 being the least significant. Refer to Endian Issues on page 4-11, which covers which parts of the MTX series use big-endian byte ordering, and which use little-endian byte ordering.
  • Page 21 <Enter>, <Return> or <CR> <CR> represents the carriage return or Enter key. CTRL represents the Control key. Execute control characters by pressing the Ctrl key and the letter simultaneously, for example, Ctrl-d. xxiii...

  • Page 22: Memory Maps

    Memory Maps Introduction This chapter briefly describes the board level hardware features of the MTX series motherboard. The chapter begins with a board level overview and features list. Memory maps are next, and are the major feature of this chapter.

  • Page 23: System Block Diagram

    Status LEDs System Block Diagram The MTX series provides the 256KB look-aside external cache option. The Falcon chip set controls the boot Flash and the ECC DRAM. The Raven ASIC functions as the 64-bit PCI host bridge and the MPIC interrupt controller.

  • Page 24: Functional Description

    Standard I/O functions are provided by the Super I/O device which resides on the ISA bus. The NVRAM/RTC and the optional synchronous serial ports also reside on the ISA bus. The general system block diagram for MTX series is shown below: Functional Description Overview The MTX is a motherboard.

  • Page 25: Figure 1-1. Mtx Series System Block Diagram

    10/100BT Serial#4 Registers RTC/NVRAM/WD PCF8584 MK48T59 Secondary EIDE Port CL-CD1283 Primary EIDE Port Super I/O Peripheral Parallel PC87308 SCSI-2 wide Serial#2 RJ45 Mouse Parallel Serial#1 Rear Panel Figure 1-1. MTX Series System Block Diagram Computer Group Literature Center Web Site...

  • Page 26: Programming Model

    Programming Model The MTX series can be populated with two IEEE1386.1 PCI Mezzanine Card (PMC) slots plus a 64-bit PCI slot, or with three 32-bit PCI slots. The 32-bit PCI slots support ATX standard I/O spacing. All slots use rear panel I/O.

  • Page 27: Table 1-3. Chrp Memory Map Example

    Board Description and Memory Maps Table 1-2. Default Processor Memory Map (Continued) Processor Address Size Definition Start FEF9 0000 FEFE FFFF 384K Not mapped FEFF 0000 FEFF FFFF Raven Registers FF00 0000 FFEF FFFF Not mapped FFF0 0000 FFFF FFFF ROM/FLASH Bank A or Bank B Notes 1.
  • Page 28 If the rom_b_rv control bit is set then this address range maps to ROM/FLASH Bank 7. The only method to generate a PCI Interrupt Acknowledge cycle (8259 IACK) is to perform a read access to the Raven’s PIACK register at 0xFEFF0030. http://www.motorola.com/computer/literature...

  • Page 29: Table 1-4. Raven Mpc Register Values For Chrp Memory Map

    Processor PREP Memory Map The Raven/Falcon chipset can be programmed for PREP-compatible memory map. The following table shows the PREP memory map of the MTX series from the point of view of the processor. Table 1-5. PREP Memory Map Example Processor Address...

  • Page 30: Table 1-6. Raven Mpc Register Values For Prep Memory Map

    Table 1-6. Raven MPC Register Values for PREP Memory Map Address Register Name Register Value FEFF 0040 MSADD0 C000 FCFF FEFF 0044 MSOFF0 & MSATT0 4000 00C2 FEFF 0048 MSADD1 0000 0000 FEFF 004C MSOFF1 & MSATT1 0000 0002 http://www.motorola.com/computer/literature...

  • Page 31: Pci Memory Maps

    Board Description and Memory Maps Table 1-6. Raven MPC Register Values for PREP Memory Map (Continued) Address Register Name Register Value FEFF 0050 MSADD2 0000 0000 FEFF 0054 MSOFF2 & MSATT2 0000 0002 FEFF 0058 MSADD3 8000 BFFF FEFF 005C MSOFF3 &...

  • Page 32: Table 1-7. Pci Chrp Memory Map Example

    0000 00FX PSADD1 0000 0000 FD00 FDFF PSOFF1 & PSATT1 0000 0000 0000 00FX PSADD2 0000 0000 0000 0000 PSOFF2 & PSATT2 0000 0000 0000 0000 PSADD3 0000 0000 0000 0000 PSOFF3 & PSATT3 0000 0000 0000 0000 http://www.motorola.com/computer/literature 1-11...

  • Page 33: Table 1-9. Pci Prep Memory Map

    Board Description and Memory Maps PCI PREP Memory Map The following table shows a PCI memory map of the MTX series that is PREP-compatible from the point of view of the PCI local bus. Table 1-9. PCI PREP Memory Map...

  • Page 34: Mpc System Bus

    Look-Aside Cache The look-aside external cache, when present, is implemented with the Glance devices. Two Glance devices operate together to provide 256KB of look-aside cache. The Glance devices are controlled via the System External Cache Control Register (SXCCR). http://www.motorola.com/computer/literature 1-13...

  • Page 35: Falcon Flash Memory

    Board Description and Memory Maps Falcon FLASH Memory The Falcon chipset supports up to two banks of FLASH memory. For the MTX each bank is 8-bits wide. Bank A FLASH size can be determined from the Memory Configuration Register. The maximum ROM/FLASH size is 64M per bank.

  • Page 36: Falcon Chipset

    Falcon and the lower Falcon. The upper Falcon connects to the upper half of the system data bus, DH00 through DH31, while the lower Falcon connects to lower half of the system data bus, DL00 through DL31. http://www.motorola.com/computer/literature 1-15...

  • Page 37: Falcon Registers

    In addition, the Falcon chipset performs the decode and control for an external register port. This function is used by the MTX series to provide the system control registers. Table 1-13. System Register Summary BIT # ---->...

  • Page 38: System Configuration Register (Syscr)

    SYSID System Identification. This field specifies the type of the overall system configuration so that the software may appropriately handle any software visible differences. For the MTX series, this field returns a value of $FB. SYSCLK System Clock Speed. This field relays the system clock speed...

  • Page 39: Memory Configuration Register (Memcr)

    Board Description and Memory Maps SYSXC Value External Look-aside Cache Size 0b0000 to 0b1011 Reserved 0b1100 0b1101 512KB 0b1110 256KB 0b1111 None P0/1STAT Processor 0/1 Status. This field is encoded as follows: P0/1STAT Value Processor 0/1 Present External In-line Cache Size 0b0000 to 0b0011 Reserved Reserved...
  • Page 40 The device width is different from the width of the FLASH bank. If the bank width is 64-bit and the device width is 16-bit then the FLASH bank consists of four FLASH devices. FLSHP[0:2] Bank A Flash memory size. This field is encoded as follows: http://www.motorola.com/computer/literature 1-19...

  • Page 41: System External Cache Control Register (Sxccr)

    Board Description and Memory Maps Flash Size FLSHP0_ FLSHP1_ FLSHP2_ 16MB 32MB 64MB No Flash System External Cache Control Register (SXCCR) The System Cache Control Register is accessed via the RD[32:39] data lines of the upper Falcon device. This 8-bit register is defined as follows: Register System External Cache Control Register - $FEF88000 Field...

  • Page 42: Processor 0 External Cache Control Register (P0Xccr)

    The Processor 0 External Cache Control Register is accessed via the RD[32:39] data lines of the upper Falcon device. This register is not implemented for systems without In-line Cache. This 8-bit register is defined as follows: Register Processor 0 External Cache Control Register - FEF88100h Field Operation Reset http://www.motorola.com/computer/literature 1-21...

  • Page 43: Processor 1 External Cache Control Register (P1Ccr)

    Board Description and Memory Maps P0XC_CFG Processor 0 External Cache Configuration Access Mode. When this bit is set, it maps the Processor 0’s external cache in Configuration Access Mode. Refer to the IBM15-C700A SLC User’s Manual for details. P0XC_DIS_ Processor 0 External Cache Disable. When this bit is cleared, it disables this cache from responding to any bus cycles.

  • Page 44: Cpu Control Register

    The PIB contains ISA Bridge I/O registers for various functions. These registers are accessible from the PCI bus. Refer to the W83C553 Data Book for details. Primary and Secondary EIDE Ports The PIB also contains the EIDE controller. Refer to the 83C553 Data Book for details. http://www.motorola.com/computer/literature 1-23...

  • Page 45: Pc87308Vul Super I/O Strapping

    1 - CS0# on CS0# pin. NVRAM/RTC & Watchdog Timer Registers The MK48T59/559 provides the MTX series with 8KB of non-volatile SRAM, a time-of-day clock, and a watchdog timer. Accesses to the MK48T59/559 are accomplished via three registers: The NVRAM/RTC Address Strobe 0 Register, the NVRAM/RTC Address Strobe 1 Register, and the NVRAM/RTC Data Port Register.

  • Page 46: Module Configuration And Status Registers

    AIX revisions. The Base Module Status Register should be used to identify the base module type and the System Configuration Register should be used to obtain information about the overall system for future releases. http://www.motorola.com/computer/literature 1-25...

  • Page 47: Base Module Feature Register

    Board Description and Memory Maps Register Old CPU Configuration Register - FE000800h Field CPUTYPE Operation Reset CPUTYPE CPU Type. This field will always read as Eh for the MTX. The System Configuration Register should be used for additional information. Base Module Feature Register The Base Module Feature Register is an 8-bit register providing the configuration information about the MTX motherboard.

  • Page 48: Base Module Status Register (Bmsr)

    Base Module Type $0 to $F7 Reserved MTX without Peripheral Parallel Port MTX with Peripheral Parallel Port $F9 to FF Reserved Extended Status Register The Extended Status Register is an 8-bit read-only register located at ISA I/O address x0951. http://www.motorola.com/computer/literature 1-27...

  • Page 49: Scsi Terminator Select

    Board Description and Memory Maps Register Extended Status Register - Offset $0951 Field Operation Reset SCSITS On board SCSI terminator status. If set, the on board terminator is enabled. If cleared, the on board terminator is disabled. SCSITP SCSI terminator power status. If set, SCSI terminator power is available.

  • Page 50: Seven-Segment Display Register

    Z85230 ESCC and Z8536 CIO Registers and Port Pins The Z85230 ESCC is used to provide the two sync/async serial ports on some MTX series models. The PCLK which can be used to derived the baud rates, is 5 MHz. Refer to the SCC User’s Manual for programming information on the Z85230 ESCC device.

  • Page 51: Z8536 Cio Port Pins

    Board Description and Memory Maps Table 1-17. Z8536/Z85230 Access Registers PCI I/O Address Function 0000 0840 Z85230: Port B (Serial Port 4) Control 0000 0841 Z85230: Port B (Serial Port 4) Data 0000 0842 Z85230: Port A (Serial Port 3) Control 0000 0843 Z85230: Port A (Serial Port 3) Data 0000 0844...

  • Page 52: Table 1-19. I2C Controller Access Registers

    Refer to the PCF8584 data sheet for additional programming information. The DIMM EEPROM addresses on the two wire serial bus are shown in Table 1-20. Table 1-19. I C Controller Access Registers PCI I/O Address Function 0000 0980 Operation Registers 0000 0981 Control/Status Register http://www.motorola.com/computer/literature 1-31...

  • Page 53: Isa Dma Channels

    Board Description and Memory Maps Table 1-20. Two Wire Serial (I C) Bus Addresses C Bus Address Function 1010000 Bank A lower DIMM 1010001 Bank A upper DIMM 1010010 Bank B lower DIMM 1010011 Bank B upper DIMM ISA DMA Channels There are seven ISA DMA channels in the PIB.

  • Page 54: Introduction

    2Raven PCI Host Bridge & Multi- Processor Interrupt Controller Introduction Overview This chapter describes the architecture and usage of the Raven, a PowerPC to PCI Local Bus Bridge ASIC. The Raven is intended to provide PowerPC microprocessor compliant devices access to devices residing on the PCI Local Bus in a very efficient manner.
  • Page 55 Raven PCI Host Bridge & Multi-Processor Interrupt Controller – 64-bit data bus, 32-bit address bus. – Optional bus arbitration logic supporting up to three bus masters. – Four independent software programmable slave map decoders. – Multi-level write post FIFO for writes to PCI. –...

  • Page 56: Block Diagram

    Block Diagram Block Diagram 1914 9610 Figure 2-1. Raven Block Diagram http://www.motorola.com/computer/literature...

  • Page 57: Functional Description

    Raven PCI Host Bridge & Multi-Processor Interrupt Controller Functional Description PPC Bus Interface The PPC Bus Interface is designed to be coupled directly to up to two PPC microprocessors as well as a memory/cache subsystem. It uses a subset of the capabilities of the PPC bus protocol.

  • Page 58: Ppc Write Posting

    PPC bus. This frees the PPC bus from waiting for the potentially long PCI arbitration and transfer. The PPC bus may be used for more useful work while the Raven manages the completion of the write posted transaction on PCI. http://www.motorola.com/computer/literature...

  • Page 59: Ppc Master

    Raven PCI Host Bridge & Multi-Processor Interrupt Controller If the write post FIFO is full, any other accesses to the Raven are delayed (AACK* will not be asserted) until there is room in the FIFO to store the complete transaction. All write posted transfers will be completed before a non-write posted read or write is begun to assure that all transfers are completed in the order issued.
  • Page 60 Raven has been programmed to respond to PCI address range $10000000 through $1001FFFF with an offset of $2000. The PPC master will perform its last read on the PPC bus at cache line address $3001FFFC or word address $3001FFF8. http://www.motorola.com/computer/literature...

  • Page 61: Table 2-2. Ppc Transfer Types

    Raven PCI Host Bridge & Multi-Processor Interrupt Controller The PPC bus transfer types generated by the PPC master depend on the PCI command code and the INV/GBL bits in the PCISATTx registers. The GBL bit determines whether or not the GBL* signal is asserted for all portions of a transaction and is fully independent of the PCI command code and INV bit.

  • Page 62: Ppc Bus Timer

    For each map, there is an independent set of attributes. These attributes are used to enable read accesses, enable write accesses, enable write posting, and define the PPC bus transfer characteristics. Each map decoder also includes a programmable 16-bit address offset. The offset is http://www.motorola.com/computer/literature...

  • Page 63: Pci Configuration Space

    Raven PCI Host Bridge & Multi-Processor Interrupt Controller added to the 16 most significant bits of the PCI address, and the result is used as the PPC address. This offset allows devices to reside at any PPC address, independent of the PCI address map. All Raven address decoders are prioritized so that programming multiple decoders to respond to the same address will not be a problem.

  • Page 64: Pci Master

    Write w/ Flush 0111 Write w/ Flush (Memory Write) Atomic 0011 Write w/ Kill (I/O Write) Graphics Write 1110 Read (Memory Read Line) Read w/ ITM 0110 Read w/ ITM Atomic (Memory Read) Graphics Read 0010 (I/O Read) http://www.motorola.com/computer/literature 2-11...

  • Page 65: Generating Pci Memory And I/O Cycles

    Raven PCI Host Bridge & Multi-Processor Interrupt Controller Generating PCI Memory and I/O Cycles Each programmable slave may be configured to generate PCI I/O or memory accesses through the MEM and IOM fields in its Attribute register as shown below. PCI Cycle Type Memory Contiguous I/O...

  • Page 66: Generating Pci Configuration Cycles

    PCI configuration space. One of the four PPC Slave Address Registers is used to gain access to $CF8 and $CFC. Note MSADD3 is initialized at reset to access PCI I/O space with an PPC address of $80000000. http://www.motorola.com/computer/literature 2-13...

  • Page 67: Generating Pci Special Cycles

    Raven PCI Host Bridge & Multi-Processor Interrupt Controller The resource at $CF8 is a 32 bit configuration address port and is referred to as the CONFIG_ADDRESS register. The resource at $CFC is a 32 bit configuration data port and is referred to as the CONFIG_DATA register. Accessing a PCI functions’s configuration port is a two step process;...

  • Page 68: When Ppc Devices Are Big-Endian

    PCI must be swapped such that PCI looks big-endian from the PPC bus’s perspective. This is shown in the following figure. PPC Bus 64-bit PCI PPC Bus 32-bit PCI 1916 9610 Figure 2-3. Big- to Little-Endian Data Swap http://www.motorola.com/computer/literature 2-15...

  • Page 69: Table 2-4. Address Modification For Little-Endian Transfers

    Raven PCI Host Bridge & Multi-Processor Interrupt Controller When PPC Devices are Little-Endian When all PPC devices are operating in little-endian mode, the PPC address must be modified to remove the exclusive-ORing applied by PPC60x processors before being passed on to PCI. The three low order processor bus address bits are exclusive-ORed with a three-bit value that depends on the length of the operand, as shown in Table...
  • Page 70 PPC master, or associated with masters other than processor 0, 1, or 2, the DFLT bit is used. One example of an error condition which cannot be associated with a particular PPC master would be a PCI system error. http://www.motorola.com/computer/literature 2-17...

  • Page 71: Pci/Ppc Contention Handling

    Raven PCI Host Bridge & Multi-Processor Interrupt Controller PCI/PPC Contention Handling The Raven has a stall detection mechanism that detects when there is a possible resource contention problem (that is, deadlock) as a result of overlapping PPC and PCI initiated transactions. The PPC Slave and the PCI Slave functions contain the logic needed to implement this feature.

  • Page 72: Transaction Ordering

    PCI bound FIFO is empty. Write posted transactions originated from the PCI bus are flushed in the following manner. The PCI slave sets a signal called ‘pcis_fbrabt’ anytime it has committed to performing a posted write http://www.motorola.com/computer/literature 2-19...

  • Page 73: Registers

    Raven PCI Host Bridge & Multi-Processor Interrupt Controller transaction. This signal will remain asserted until the PPC bound FIFO count has reached zero. The PPC slave address decode logic settles out several clocks after the assertion of TS*, at which time the PPC slave can determine the transaction type.

  • Page 74: Ppc Registers

    $FEFF0000 VENID DEVID $FEFF0004 REVID $FEFF0008 GCSR FEAT $FEFF000C $FEFF0010 PADJ $FEFF0014 $FEFF0018 $FEFF001C $FEFF0020 ERRTST ERREN $FEFF0024 ERRST $FEFF0028 ERRAD $FEFF002C ERRAT $FEFF0030 PIACK $FEFF0034 $FEFF0038 $FEFF003C $FEFF0040 PPCSADD0 $FEFF0044 PPCSOFF0 PPCSATT0 $FEFF0048 PPCSADD1 $FEFF004C PPCSOFF1 PPCSATT1 http://www.motorola.com/computer/literature 2-21...

  • Page 75: Table 2-5. Raven Ppc Register Map

    VENID Vendor ID. This register identifies the manufacturer of the device. This identifier is allocated by the PCI SIG to ensure uniqueness. $1057 has been assigned to Motorola. This register is duplicated in the PCI Configuration Registers. DEVID Device ID. This register identifies this particular device. The Raven will always return $4801.

  • Page 76: Revision Id Register

    PPC Devices are Little-Endian on page 2-16. When LEND is clear, the PPC bus is operating in big-endian mode, and all data to/from PCI is swapped as described in the section When PPC Devices are Big-Endian on page 2-15. http://www.motorola.com/computer/literature 2-23...
  • Page 77 Raven PCI Host Bridge & Multi-Processor Interrupt Controller PCIFBR PCI Flush Before Read. If set, the Raven will guarantee that all PPC initiated read transactions will be completed before any PPC initiated read transactions will be allowed to complete. When PCIFBR is clear, there will be no correlation between these transaction types and their order of completion.

  • Page 78: Prescaler Adjust Register

    1 MHz. The scale factor is calculated as follows: PADJ = 256 - Clk, where Clk is the frequency of the CLK input in MHz. The following table shows the scale factors for some common CLK frequencies. http://www.motorola.com/computer/literature 2-25...

  • Page 79: Ppc Error Enable Register

    Raven PCI Host Bridge & Multi-Processor Interrupt Controller Frequency PADJ PPC Error Enable Register Address $FEFF0020 0 1 2 3 4 5 6 7 8 9 Name ERRTST ERREN Reset Address DPEx Data Parity Error Enable. These bits are used for test reasons to purposely inject data parity errors whenever Raven is sourcing PPC data.
  • Page 80 PDPEI PPC Data Parity Error Interrupt Enable. When this bit is set, the PDPE bit in the ERRST register will be used to assert an interrupt through the OpenPIC interrupt controller. When this bit is clear, no interrupt will be asserted. http://www.motorola.com/computer/literature 2-27...

  • Page 81: Ppc Error Status Register

    Raven PCI Host Bridge & Multi-Processor Interrupt Controller PERRI PCI Parity Error Interrupt Enable.When this bit is set, the PERR bit in the ERRST register will be used to assert an interrupt through the OpenPIC interrupt controller. When this bit is clear, no interrupt will be asserted.
  • Page 82 ERREN register is set, the assertion of this bit will assert MCHK to the master designated by the MID field in the ERRAT register. When the SMAI bit in the ERREN register is set, the assertion of this bit will assert an interrupt through the OpenPIC interrupt controller. http://www.motorola.com/computer/literature 2-29...

  • Page 83: Ppc Error Address Register

    Raven PCI Host Bridge & Multi-Processor Interrupt Controller RTA PCI Master Received Target Abort. This bit is set when the PCI master receives target abort to terminate a PCI transaction. It may be cleared by writing it to a 1; writing it to a 0 has no effect. When the RTAM bit in the ERREN register is set, the assertion of this bit will assert MCHK to the master designated by the MID field in the ERRAT register.
  • Page 84 * Refer to PowerPC documents listed in Table A-2 on page A-2. If the SMA or RTA bit are set the register is defined by the following table. Address $FEFF002C 0 1 2 3 4 5 6 7 8 9 Name MERAT Operation Reset http://www.motorola.com/computer/literature 2-31...

  • Page 85: Pci Interrupt Acknowledge Register

    Raven PCI Host Bridge & Multi-Processor Interrupt Controller WP Write Post Completion. This bit is set when the PCI master detects an error while completing a write post transfer. MIDx PPC Master ID. This field contains the ID of the PPC master which originated the transfer in which the error occurred.

  • Page 86: Ppc Slave Address (0,1 And 2) Registers

    The value of this field will be compared with the upper 16 bits of the incoming PPC address. PPC Slave Address (3) Register Address MSADD3 - $FEFF0058 0 1 2 3 4 5 6 7 8 9 Name MSADD3 START Operation Reset $8000 $8080 http://www.motorola.com/computer/literature 2-33...

  • Page 87: Ppc Slave Offset/Attribute (0,1 And 2) Registers

    Raven PCI Host Bridge & Multi-Processor Interrupt Controller MSADD3, MSOFF3, and MSATT3 represent the only register group which can be used to initiate access to the PCI Configuration Address ($80000CF8) and Configuration Data ($80000CFC) registers. Note that this implies that MSxxx3 also represents the generation of PCI Special Cycles.

  • Page 88: Ppc Slave Offset/Attribute (3) Registers

    PPC slave will generate PCI I/O cycles using contiguous addressing. This field only has meaning when the MEM bit is clear. PPC Slave Offset/Attribute (3) Registers Address MSOFF3/MSATT3 - $FEFF005C 0 1 2 3 4 5 6 7 8 9 Name MSOFF3 MSATT3 Operation Reset $8000 http://www.motorola.com/computer/literature 2-35...

  • Page 89: General Purpose Registers

    Raven PCI Host Bridge & Multi-Processor Interrupt Controller MSOFF3 PPC Slave Offset. This register contains a 16-bit offset that is added to the upper 16 bits of the PPC address to determine the PCI address used for transfers from the PPC bus to PCI. This offset allows PCI resources to reside at addresses that would not normally be visible from the PPC bus.

  • Page 90: Table 2-6. Raven Pci Configuration Register Map

    Table 2-6. Raven PCI Configuration Register Map <--- Bit 0 9 8 7 6 5 4 3 2 1 0 DEVID VENID PSTAT PCOMM CLASS REVID HEADER IOBASE MEMBASE $18 - $7F PSADD0 PSOFF0 PSATT0 PSADD1 PSOFF1 PSATT1 PSADD2 PSOFF2 PSATT2 PSADD3 PSOFF3 PSATT3 http://www.motorola.com/computer/literature 2-37...

  • Page 91: Table 2-7. Raven Pci I/O Register Map

    VENID Vendor ID. This register identifies the manufacturer of the device. This identifier is allocated by the PCI SIG to ensure uniqueness. $1057 has been assigned to Motorola. This register is duplicated in the PPC Registers. DEVID Device ID. This register identifies the particular device. The Raven will always return $4801.

  • Page 92: Pci Command/ Status Registers

    Raven will never drive SERR*. If set, the Raven will drive SERR* active when a system error is detected. FAST Fast Back-to-Back Capable. This bit indicates that the Raven is capable of accepting fast back-to-back transactions with different targets. http://www.motorola.com/computer/literature 2-39...

  • Page 93: Revision Id/ Class Code Registers

    Raven PCI Host Bridge & Multi-Processor Interrupt Controller DPAR Data Parity Detected. This bit is set when three conditions are met: 1) the Raven asserted PERR* itself or observed PERR* asserted; 2) the Raven was the PCI master for the transfer in which the error occurred; 3) the PERR bit in the PCI Command Register is set.

  • Page 94: Header Type Register

    Single Function Configuration Header I/O Base Register Offset 0 9 8 7 6 5 4 3 2 1 0 Name IOBASE IOBA Operation Reset $0000 $0000 This register controls the mapping of the MPIC control registers in PCI I/O space. http://www.motorola.com/computer/literature 2-41...

  • Page 95: Memory Base Register

    Raven PCI Host Bridge & Multi-Processor Interrupt Controller IO/MEM IO Space Indicator. This bit is hard-wired to a logic one to indicate PCI I/O space. RES Reserved. This bit is hard-wired to zero. IOBA I/O Base Address. These bits define the I/O space base address of the MPIC control registers.

  • Page 96: Pci Slave Address (0,1,2 And 3) Registers

    END End Address. This field determines the end address of a particular memory area on the PCI bus which will be used to access PPC bus resources. The value of this field will be compared with the upper 16 bits of the incoming PCI address. http://www.motorola.com/computer/literature 2-43...

  • Page 97: Pci Slave Attribute/ Offset (0,1,2 And 3) Registers

    Raven PCI Host Bridge & Multi-Processor Interrupt Controller PCI Slave Attribute/ Offset (0,1,2 and 3) Registers Offset PSATT0/PCISOFF0 - $84 PSATT1/PCISOFF1 - $8C PSATT2/PCISOFF2 - $94 PSATT3/PCISOFF3 - $9C 0 9 8 7 6 5 4 3 2 1 0 Name PCISOFFx PSATTx...

  • Page 98: Config_Address

    PCI configuration address and data space without changing Raven registers. PCI I/O CONFIG_ADDRESS Register Offset $CF8 0 9 8 7 6 5 4 3 2 1 0 Name CONFIG_ADDRESS Operation Reset LEND = 0 PPC[39:32] PPC[47:40] PPC[55:48] PPC[63:56] LEND = 1 PPC[31:24] PPC[23:16] PPC[15:8] PPC[7:0] http://www.motorola.com/computer/literature 2-45...
  • Page 99 Raven PCI Host Bridge & Multi-Processor Interrupt Controller REG Register Number. For PCI Configuration cycles, bits 7 through 2 identify the target double word within the target function’s configuration space. Bits 1 and 0 must always be zero for a type 0 configuration cycle. These bits are copied to the PCI AD bus during the address phase on a Configuration cycle.This field must be all zeros for Special cycles.

  • Page 100: Pci I/O Config_Data Register

    Support for 16 external interrupts Support for 15 programmable Interrupt & Processor Task priority levels Support for the connection of an external 8259 for ISA/AT compatibility Distributed interrupt delivery for external I/O interrupts Direct/Multicast interrupt delivery for Interprocessor and timer interrupts http://www.motorola.com/computer/literature 2-47...

  • Page 101: Architecture

    Raven PCI Host Bridge & Multi-Processor Interrupt Controller Four Interprocessor Interrupt sources Four timers Processor initialization control Architecture The Raven PCI Slave implements two address decoders for placing the Raven MPIC registers in PCI IO or PCI Memory space. Access to these registers require MPC and PCI bus mastership.

  • Page 102: Processor's Current Task Priority

    Interprocessor Interrupts (IPI) Processor 0 and 1 can generate interrupts which are targeted for the other processor or both processors. There are four Interprocessor Interrupts (IPI) channels. The interrupts are initiated by writing a bit in the IPI dispatch http://www.motorola.com/computer/literature 2-49...

  • Page 103: Compatibility

    Raven PCI Host Bridge & Multi-Processor Interrupt Controller registers. If subsequent IPIs are initiated before the first is acknowledged, only one IPI will be generated. The IPI channels deliver interrupts in the Direct Mode and can be directed to more than one processor. 8259 Compatibility The Raven MPIC provides a mechanism to support PC-AT compatible chip sets using the 8259 interrupt controller architecture.

  • Page 104: Interrupt Delivery Modes

    If both destination bits are set for each processor, the interrupt will be delivered to the processor that has a lower task register priority. http://www.motorola.com/computer/literature 2-51...

  • Page 105: Block Diagram Description

    Raven PCI Host Bridge & Multi-Processor Interrupt Controller Note Because a deadlock condition can occur when the task register priorities for each processor are the same and both processors are targeted for interrupt delivery, the interrupt will be delivered to processor 0 or processor 1 as determined by the TIE mode.

  • Page 106: Figure 2-4. Raven Mpic Block Diagram

    Raven Interrupt Controller Implementation interrupt signals Program Visible Registers Interrupt Interrupt Selector_1 Selector_0 IRR_1 IRR_0 ISR_1 ISR_0 Interrupt Router INT1 INT 0 1917 9610 Figure 2-4. Raven MPIC Block Diagram http://www.motorola.com/computer/literature 2-53...

  • Page 107: Program Visible Registers

    Raven PCI Host Bridge & Multi-Processor Interrupt Controller Program Visible Registers These are the registers which software can access. They are described in detail in the Register section. Interrupt Pending Register (IPR) The interrupt signals to Raven MPIC are qualified and synchronized to the clock by the IPR.

  • Page 108: Interrupt Request Register (Irr)

    IPR bit is cleared when the vector for that interrupt is returned when the Interrupt Acknowledge register is examined. On the other hand, if the interrupt is a direct/multicast class interrupt, there are two bits in the IPR associated with this interrupt. One bit for each processor. http://www.motorola.com/computer/literature 2-55...
  • Page 109 Raven PCI Host Bridge & Multi-Processor Interrupt Controller Then one of these bits are delivered to each Interrupt Selector. Since this interrupt source can be multicast, each of these IPR bits must be cleared separately when the vector is returned for that interrupt to a particular processor.

  • Page 110: Mpic Registers

    256KB range. If the index into that 256KB block does not decode a valid Raven MPIC register address, the logic will return $00000000. The registers are 8, 16, or 32 bits accessible. http://www.motorola.com/computer/literature 2-57...

  • Page 111: Table 2-8. Raven Mpic Register Map

    Raven PCI Host Bridge & Multi-Processor Interrupt Controller Table 2-8. Raven MPIC Register Map 0 9 8 7 6 5 4 3 2 1 0 FEATURE REPORTING REGISTER 0 $01000 GLOBAL CONFIGURATION REGISTER 0 $01020 MPIC VENDOR IDENTIFICATION REGISTER $01080 PROCESSOR INIT REGISTER $01090 IPI0 VECTOR-PRIORITY REGISTER...
  • Page 112 INT. SRC. 10 VECTOR-PRIORITY REGISTER $10140 INT. SRC. 10 DESTINATION REGISTER $10150 INT. SRC. 11 VECTOR-PRIORITY REGISTER $10160 INT. SRC. 11 DESTINATION REGISTER $10170 INT. SRC. 12 VECTOR-PRIORITY REGISTER $10180 INT. SRC. 12 DESTINATION REGISTER $10190 INT. SRC. 13 VECTOR-PRIORITY REGISTER $101a0 http://www.motorola.com/computer/literature 2-59...
  • Page 113 Raven PCI Host Bridge & Multi-Processor Interrupt Controller Table 2-8. Raven MPIC Register Map (Continued) 0 9 8 7 6 5 4 3 2 1 0 INT. SRC. 13 DESTINATION REGISTER $101b0 INT. SRC. 14 VECTOR-PRIORITY REGISTER $101c0 INT. SRC. 14 DESTINATION REGISTER $101d0 INT.

  • Page 114: Feature Reporting Register

    Version level of 03 is used for this release of the MPIC specification. Global Configuration Register Offset $01020 0 9 8 7 6 5 4 3 2 1 0 Name GLOBAL CONFIGURATION Operation Reset http://www.motorola.com/computer/literature 2-61...
  • Page 115 Raven PCI Host Bridge & Multi-Processor Interrupt Controller R RESET CONTROLLER. Writing a one to this bit forces the controller logic to be reset. This bit is cleared automatically when the reset sequence is complete. While this bit is set, the values of all other register are undefined.

  • Page 116: Vendor Identification Register

    1. Writing a 0 to it will negate the SRESET signal. P0 PROCESSOR 0. Writing a 1 to P0 will assert the Soft Reset input of processor 0. Writing a 0 to it will negate the SRESET signal. The Soft Reset input to the 604 is negative edge-sensitive. http://www.motorola.com/computer/literature 2-63...

  • Page 117: Ipi Vector/Priority Registers

    Raven PCI Host Bridge & Multi-Processor Interrupt Controller IPI Vector/Priority Registers Offset IPI 0 - $010A0 IPI 1 - $010B0 IPI 2 - $010C0 IPI 3 - $010D0 0 9 8 7 6 5 4 3 2 1 0 Name IPI VECTOR/PRIORITY PRIOR VECTOR...

  • Page 118: Spurious Vector Register

    Following reset, this register contains zero. system initialization code must initialize this register to one-eighth the MPIC clock frequency. For the Raven implementation of MPIC, a typical value would be $7de290 which is 66/8 MHz or 8.25 MHz. http://www.motorola.com/computer/literature 2-65...

  • Page 119: Timer Current Count Registers

    Raven PCI Host Bridge & Multi-Processor Interrupt Controller Timer Current Count Registers Offset Timer 0 - $01100 Timer 1 - $01140 Timer 2 - $01180 Timer 3 - $011C0 0 9 8 7 6 5 4 3 2 1 0 Name TIMER CURRENT COUNT Operation...

  • Page 120: Timer Vector/Priority Registers

    The ACT bit is set to a one when its associated bit in the Interrupt Pending Register or In-Service Register is set. PRIOR Interrupt priority 0 is the lowest and 15 is the highest. Note that a priority level of 0 will not enable interrupts. http://www.motorola.com/computer/literature 2-67...

  • Page 121: Timer Destination Registers

    Raven PCI Host Bridge & Multi-Processor Interrupt Controller VECTOR This vector is returned when the Interrupt Acknowledge register is examined upon acknowledgement of the interrupt associated with this vector. Timer Destination Registers Offset Timer 0 - $01130 Timer 1 - $01170 Timer 2 - $011B0 Timer 3 - $011F0 0 9 8 7 6 5 4 3 2 1 0...

  • Page 122: External Source Vector/Priority Registers

    15, setting this bit to a zero enables positive edge triggered interrupts. Setting this bit to a one enables active low level triggered interrupts. PRIOR Interrupt priority 0 is the lowest and 15 is the highest. Note that a priority level of 0 will not enable interrupts. http://www.motorola.com/computer/literature 2-69...

  • Page 123: External Source Destination Registers

    Raven PCI Host Bridge & Multi-Processor Interrupt Controller VECTOR This vector is returned when the Interrupt Acknowledge register is examined upon acknowledgement of the interrupt associated with this vector. External Source Destination Registers Offset Int Src 0 - $10010 Int Src 2 -> Int Src 15 - $10030 -> $101F0 0 9 8 7 6 5 4 3 2 1 0 Name EXTERNAL SOURCE DESTINATION...

  • Page 124: Raven-Detected Errors Vector/Priority Register

    PRIOR Interrupt priority 0 is the lowest and 15 is the highest. Note that a priority level of 0 will not enable interrupts. VECTOR This vector is returned when the Interrupt Acknowledge register is examined upon acknowledgedment of the interrupt associated with this vector. http://www.motorola.com/computer/literature 2-71...

  • Page 125: Raven-Detected Errors Destination Register

    Raven PCI Host Bridge & Multi-Processor Interrupt Controller Raven-Detected Errors Destination Register Offset $10210 0 9 8 7 6 5 4 3 2 1 0 Name RAVEN DETECTED ERROR DESTINATION Operation Reset This register indicates the possible destinations for the Raven detected error interrupt source.

  • Page 126: Interrupt Task Priority Registers

    $F when it is reset or when the Init bit associated with this processor is written to a one. Interrupt Acknowledge Registers Offset Processor 0 $200A0 Processor 1 $210A0 0 9 8 7 6 5 4 3 2 1 0 Name VECTOR Operation Reset http://www.motorola.com/computer/literature 2-73...

  • Page 127: End-Of-Interrupt Registers

    Raven PCI Host Bridge & Multi-Processor Interrupt Controller On PowerPC-based systems, Interrupt Acknowledge is implemented as a read request to a memory-mapped Interrupt Acknowledge register. Reading the Interrupt Acknowledge register returns the interrupt vector corresponding to the highest priority pending interrupt. Reading this register also has the following side effects.
  • Page 128 8259 are enabled, the interrupt handler issues an EOI request to the 8259. Normally, interrupts from ISA devices are connected to the 8259 interrupt controller. ISA devices typically rely on the 8259 Interrupt Acknowledge to flush buffers between the ISA device and system http://www.motorola.com/computer/literature 2-75...

  • Page 129: Reset State

    Raven PCI Host Bridge & Multi-Processor Interrupt Controller memory. If interrupts from ISA devices are directly connected to the Raven MPIC (bypassing the 8259), the device driver interrupt service routine must read status from the ISA device to ensure buffers between the device and system memory are flushed. Reset State After a power-on reset the Raven MPIC state is: Current task priority for all CPUs set to 15.

  • Page 130: Dynamically Changing I/O Interrupt Configuration

    8259 Mode The 8259 mode bits control the use of an external 8259 pair for PC-AT compatibility. Following a reset, this mode is set for pass-through, which essentially disables the advanced controller and passes an 8259 input on http://www.motorola.com/computer/literature 2-77...

  • Page 131: Current Task Priority Level

    Raven PCI Host Bridge & Multi-Processor Interrupt Controller external interrupt source 0 directly through to processor zero. During interrupt controller initialization this channel should be programmed for mixed mode in order to take advantage of the interrupt delivery modes. Current Task Priority Level Each processor has a separate Current Task Priority Level register.

  • Page 132: Introduction

    3Falcon ECC Memory Controller Chip Set Introduction The Falcon DRAM controller ASIC is designed for the PowerPC families of boards. It is used in sets of two to provide the interface between the PowerPC 60x bus (also called MPC60x bus or MPC bus) and a 144-bit ECC-DRAM memory system.

  • Page 133: Block Diagrams

    Falcon ECC Memory Controller Chip Set – Does not provide TEA_ on Double-Bit Error. (Chip has no TEA_ pin.) ROM/Flash Interface – Two blocks with each block being 16 bits wide (8 bits per Falcon), or 64 bits wide (32 bits per Falcon). –...

  • Page 134: Figure 3-1. Falcon Pair Used With Dram In A System

    Upper DRAM Data (64 Bits) Data Upper DRAM Address & Control Upper PowerPC Data (32 Bits) Upper PowerPC Check Upper DRAM Data Parity (4 Bits) Check-bits (8 Bits) 1900 9609 Figure 3-1. Falcon Pair Used with DRAM in a System http://www.motorola.com/computer/literature...

  • Page 135: Figure 3-2. Falcon Internal Data Paths (Simplified)

    Falcon ECC Memory Controller Chip Set PowerPC DRAM Side Side (64 Bits) Latched D (64 Bits) (64 Bits) (8 Bits) (8 Bits) (8 Bits) Uncorrected Data (64 Bits) Figure 3-2. Falcon Internal Data Paths (Simplified) Computer Group Literature Center Web Site...

  • Page 136: Figure 3-3. Overall Dram Connections

    Block C Block A Block B Block D Lower Lower Lower Lower BD_RAS_/CAS_ AC_RAS_/CAS_ RA/OE_/WE_ UPPER RD0-63 FALCON CKD0-7 DRAM DRAM DRAM DRAM Block C Block A Block B Block D Upper Upper Upper Upper Figure 3-3. Overall DRAM Connections http://www.motorola.com/computer/literature...

  • Page 137: Functional Description

    Falcon ECC Memory Controller Chip Set Functional Description The following sections describe the logical function of the ASIC. The Falcon is designed to be used as a set of two chips. A pair of Falcons works with x1 or wider DRAM memory devices to form a memory system for the PowerPC 60x bus.

  • Page 138: Table 3-1. Powerpc 60X Bus To Dram Access Timing When Configured For 70Ns Fast

    ACCESS TYPE Total Clocks Beat Beat Beat Beat 4-Beat Read after Idle (Quad-word aligned) 4-Beat Read after Idle (Quad-word misaligned) 4-Beat Read after 4-Beat Read 14/8 (Quad-word aligned) 4-Beat Read after 4-Beat Read 13/8 (misaligned) 4-Beat Write after Idle http://www.motorola.com/computer/literature...

  • Page 139: Table 3-2. Powerpc 60X Bus To Dram Access Timing When Configured For 60Ns Fast

    Falcon ECC Memory Controller Chip Set Table 3-1. PowerPC 60x Bus to DRAM Access Timing when Configured for 70ns Fast Page Devices (Continued) CLOCK PERIODS REQUIRED FOR: ACCESS TYPE Total Clocks Beat Beat Beat Beat 4-Beat Write after 4-Beat Write 10/6 13/9 (Quad-word aligned)
  • Page 140 1. These numbers assume that the PowerPC 60x bus master is doing address pipelining with TS_ occurring at the minimum time after AACK_ is asserted. Also the two numbers shown in the 1st beat column are for page miss/page hit. http://www.motorola.com/computer/literature...

  • Page 141: Table 3-3. Powerpc 60X Bus To Dram Access Timing When Configured For 50Ns Edo Devices

    Falcon ECC Memory Controller Chip Set 2. In some cases, the numbers shown are averages and specific instances may be longer or shorter. Table 3-3. PowerPC 60x Bus to DRAM Access Timing when Configured for 50ns EDO Devices CLOCK PERIODS REQUIRED FOR: ACCESS TYPE Total Clocks...

  • Page 142: Table 3-4. Powerpc 60X Bus To Rom/Flash Access Timing When Configured For 180Ns Devices

    CLOCK PERIODS REQUIRED FOR: Total Clocks 1st Beat 2nd Beat 3rd Beat 4th Beat Bits Bits Bits Bits Bits Bits Bits Bits Bits Bits 4-Beat Read 4-Beat Write 1-Beat Read (1 byte) 1-Beat Read (2 to 8 bytes) 1-Beat Write http://www.motorola.com/computer/literature 3-11...

  • Page 143: Table 3-6. Powerpc 60X Bus To Rom/Flash Access Timing When Configured For 75Ns Devices

    Falcon ECC Memory Controller Chip Set Table 3-6. PowerPC 60x Bus to ROM/Flash Access Timing when configured for 75ns Devices ACCESS TYPE CLOCK PERIODS REQUIRED FOR: Total Clocks 1st Beat 2nd Beat 3rd Beat 4th Beat Bits Bits Bits Bits Bits Bits Bits...

  • Page 144: Responding To Address Transfers

    60x data byte lanes and the corresponding DP signal for odd parity. If any of the four lanes has even parity, that Falcon logs the error in the CSR and can generate a machine check if so enabled. In addition to http://www.motorola.com/computer/literature 3-13...

  • Page 145: Cache Coherency

    Falcon ECC Memory Controller Chip Set logging the error, that Falcon also pulses its DPERR_ signal true for the duration of one clock period, two clock periods after the TA_ during which the error data is captured. While normal (default) operation is for the Falcon to check data parity only on writes to itself, it can also be programmed to check data parity on all reads or writes to any device on the 60x bus Cache Coherency...

  • Page 146: Cycle Types

    144 bits back to DRAM. Error Reporting The Falcon pair checks data from the DRAM during single- and four-beat reads, during single-beat writes, and during scrubs. Table 3-8 shows the actions it takes for different errors during these accesses. http://www.motorola.com/computer/literature 3-15...
  • Page 147 Falcon ECC Memory Controller Chip Set Note The Falcon pair does not assert TEA_ on double-bit errors. In fact, the Falcon pair does not have a TEA_ signal pin and it assumes that the system does not implement TEA_. The Falcon 3-16 Computer Group Literature Center Web Site...

  • Page 148: Table 3-8. Error Reporting

    Triple- (or Some of these errors are detected correctly and are treated the same as double-bit greater) errors. The rest could show up as “no error” or “single-bit error”, both of which Bit Error are incorrect. http://www.motorola.com/computer/literature 3-17...

  • Page 149: Error Logging

    Falcon ECC Memory Controller Chip Set Notes 1. No opportunity for error since no read of DRAM occurs during a four-beat write. 2. The recommended connection for Falcon is for WE* to connect from upper Falcon to both upper and lower DRAM’s of banks A and B and for WE* of lower Falcon to connect to both upper and lower DRAM’s of banks C and D.
  • Page 150 When the width status bit is set, the block’s ROM/Flash is considered to be 64 bits wide, where each Falcon interfaces with 32 bits. In this mode, the following rules are enforced: c. only aligned, 4-byte writes should be attempted (all other sizes are ignored), and http://www.motorola.com/computer/literature 3-19...

  • Page 151: Table 3-9. Powerpc 60X To Rom/Flash Address Mapping When Rom/Flash Is

    Falcon ECC Memory Controller Chip Set d. all reads are allowed (multiple accesses to the ROM/Flash device are performed for burst reads). More information about ROM/Flash is found in the section on the Programming Model. In order to place code correctly in the ROM/Flash devices, address mapping information is required.

  • Page 152: Table 3-10. Powerpc 60X To Rom/Flash Address Mapping When Rom/Flash Is 64 Bits Wide (32 Bits Per Falcon)

    $000000 Lower $X0000006 $000000 Lower $X0000007 $000000 Lower $X0000008 $000001 Upper $X0000009 $000001 Upper $X000000A $000001 Upper $X000000B $000001 Upper $X000000C $000001 Lower $X000000D $000001 Lower $X000000E $000001 Lower $X000000F $000001 Lower $X3FFFFF0 $7FFFFE Upper $X3FFFFF1 $7FFFFE Upper http://www.motorola.com/computer/literature 3-21...

  • Page 153: Refresh/Scrub

    Falcon ECC Memory Controller Chip Set Table 3-10. PowerPC 60x to ROM/Flash Address Mapping when ROM/Flash is 64 Bits Wide (32 Bits per Falcon) (Continued) PowerPC 60x A0-A31 ROM/Flash A22-A0 ROM/Flash Selected $X3FFFFF2 $7FFFFE Upper $X3FFFFF3 $7FFFFE Upper $X3FFFFF4 $7FFFFE Lower $X3FFFFF5 $7FFFFE...

  • Page 154: Blocks A And/Or B Present, Blocks C And/Or D Present

    During scrub cycles, if the SWEN bit is cleared, the Falcon pair does not perform the write portion of the read-modify write cycle. If the SWEN bit is set, the Falcon pair does perform the write unless it encounters a double- bit error during the read. http://www.motorola.com/computer/literature 3-23...

  • Page 155: Chip Defaults

    Falcon ECC Memory Controller Chip Set If so enabled, single- and double-bit scrub errors are logged, and the PowerPC 60x bus master is notified via interrupt. Chip Defaults Some jumper option kinds of parameters need to be configured by software in the Falcon pair. These parameters include DRAM and ROM/Flash attributes.

  • Page 156: Figure 3-4. Data Path For Reads From The Falcon Internal Csrs

    Falcon while CSR data read on the lower half of the data bus comes from the lower Falcon. See the figure below. MPC60x Master Upper FALCON Lower FALCON 1903 9609 Figure 3-4. Data Path for Reads from the Falcon Internal CSRs http://www.motorola.com/computer/literature 3-25...

  • Page 157: Figure 3-5. Data Path For Writes To The Falcon Internal Csrs

    Falcon ECC Memory Controller Chip Set For writes, internal register data written on the upper half of the data bus goes to the upper Falcon and is automatically copied by hardware to the lower Falcon. Internal register data written on the lower half of the data bus does not go to either Falcon in the pair, but the access is terminated normally with TA_.

  • Page 158: Figure 3-6. Memory Map For Byte Reads To The Csr

    Upper Falcon $FEF80002 Upper Falcon $FEF80003 Lower Falcon $FEF80004 Lower Falcon $FEF80005 Lower Falcon $FEF80006 Lower Falcon $FEF80007 Upper Falcon $FEF80008 Upper Falcon $FEF80009 Lower Falcon $FEF807FF 1905 9609 Figure 3-6. Memory Map for Byte Reads to the CSR http://www.motorola.com/computer/literature 3-27...

  • Page 159: Figure 3-7. Memory Map For Byte Writes To The Internal Register Set

    Falcon ECC Memory Controller Chip Set $FEF80000 Both Falcons Both Falcons $FEF80001 Both Falcons $FEF80002 Writes not allowed Here Both Falcons $FEF80003 $FEF80004 $FEF80005 $FEF80006 $FEF80007 Both Falcons $FEF80008 Both Falcons $FEF80009 $FEF807FF 1906 9609 Figure 3-7. Memory Map for Byte Writes to the Internal Register Set 3-28 Computer Group Literature Center Web Site...

  • Page 160: Figure 3-8. Memory Map For 4-Byte Reads To The Csr

    1907 9609 Figure 3-8. Memory Map for 4-Byte Reads to the CSR Writes not allowed Here $FEF80000 Both Falcons $FEF80004 Both Falcons $FEF80008 $FEF8000C $FEF807FC 1908 9609 Figure 3-9. Memory Map for 4-Byte Writes to the Internal Register Set http://www.motorola.com/computer/literature 3-29...

  • Page 161: Table 3-11. Register Summary

    Falcon ECC Memory Controller Chip Set Register Summary Table 3-11 shows a summary of the CSR. Note The table only shows addresses for accesses to the upper Falcon. To get the addresses for accesses to the lower Falcon, add 4 to the address shown.
  • Page 162 Notes 1. All shaded bit fields are reserved and read as zeros. 2. All status bits are shown in italics. 3. All control bits are shown with underline. 4. All control-and-status bits are shown with italics and underline. http://www.motorola.com/computer/literature 3-31...

  • Page 163: Detailed Register Bit Descriptions

    READ ONLY READ ONLY Reset VENDID This read-only register contains the value $1057. It is the vendor number assigned to Motorola Inc. DEVID This read-only register contains the value $4802. It is the device number for the Falcon. 3-32 Computer Group Literature Center Web Site...

  • Page 164: Revision Id/General Control Register

    When adis is clear, fast page mode operation is used for back-to-back pipelined accesses to the same page within DRAM. When it is set, RAS is cycled between accesses. This bit should normally be cleared unless the Falcon has a problem operating that way. http://www.motorola.com/computer/literature 3-33...

  • Page 165: Table 3-12. Ram Spd1,Ram Spd0 And Dram Type

    Falcon ECC Memory Controller Chip Set ram fref Some DRAMs require that they be refreshed at the rate of 7.8µs per row rather than the standard 15.6µs per row. If any of the DRAM devices require the higher rate, then the ram fref bit should be left set, otherwise, it can be cleared.

  • Page 166: Dram Attributes Register

    CLK Frequency Register (offset $FEF80020) is within a factor of 2 of matching the actual 60x clock frequency ram a/b/c/d en ram a/b/c/d en enables accesses to the corresponding block of DRAM when set, and disables them when cleared. http://www.motorola.com/computer/literature 3-35...

  • Page 167: Table 3-13. Block_A/B/C/D Configurations

    Falcon ECC Memory Controller Chip Set ram a/b/c/d siz0-2 These control bits define the size of their corresponding block of DRAM. Table 3-13 shows the block configuration assumed by the Falcon pair for each value of ram siz0-ram siz2. Table 3-13. Block_A/B/C/D Configurations ram a/b/c/d Block Devices Used...

  • Page 168: Dram Base Register

    READ ZERO Reset 42 P CLK FREQUENCY These bits should be programmed with the hexadecimal value of the operating CLOCK frequency in MHz (that is, $42 for 66 MHz). When these bits are programmed this way, the chip’s http://www.motorola.com/computer/literature 3-37...

  • Page 169: Ecc Control Register

    Falcon ECC Memory Controller Chip Set prescale counter produces a 1 MHz output. The output of the chip prescale counter is used by the refresher/scrubber and the 32-bit counter. After power-up, this register is initialized to $42 (for 66MHz). por por is set by the occurrence of power up reset. It is cleared by writing a one to it.
  • Page 170 To avoid this, it is recommended that the derc bit also be set while the rwcb bit is set. A possible sequence for performing read-write check-bits is as follows: http://www.motorola.com/computer/literature 3-39...
  • Page 171 Falcon ECC Memory Controller Chip Set 1. Disable scrub writes by clearing the swen bit if it is set. 2. Make sure software is not using DRAM at this point, because while rwcb is set, DRAM will not function as normal memory. 3.

  • Page 172: Error Logger Register

    Falcon, and status read from the lower Falcon pertains to the lower Falcon. Unlike most of the other registers, however, it is normal for this status to differ between the two. This is due to the fact that each Falcon is connected http://www.motorola.com/computer/literature 3-41...
  • Page 173 Falcon ECC Memory Controller Chip Set to its own set of DRAMs. The upper Falcon can log an error during a cycle and the local Falcon not, or vice-versa. Or they can both log an error during the same cycle and have the attributes of the errors differ. Because of the above, software needs to monitor both the upper and lower Falcon’s Error Logger and Error Address Registers.
  • Page 174 It is cleared by power-up reset and by software writing all zeros to it. When SBE COUNT rolls over from $FF to $00, its Falcon sets the scof bit. It also pulses the INT_ signal low if the scien bit is set. http://www.motorola.com/computer/literature 3-43...

  • Page 175: Error_Address Register

    Falcon ECC Memory Controller Chip Set Error_Address Register Address $FEF80038 Name ERROR_ADDRESS Operation READ ONLY Reset ERROR_ADDRESS These bits reflect the value that corresponds to bits 0-27 of the PowerPC 60x address bus when their Falcon last logged an error during a PowerPC access to DRAM. They reflect the value of the DRAM row and column addresses if the error was logged during a scrub cycle.

  • Page 176: Table 3-14. Rtest Encodings

    0s and continues counting. ROW ADDRESS is readable and writable for test purposes. Note Within each block, the most significant bits of ROW ADDRESS are used only when their DRAM devices are large enough to require them. http://www.motorola.com/computer/literature 3-45...

  • Page 177: Rom A Base/Size Register

    Falcon ECC Memory Controller Chip Set COL ADDRESS These bits form the column address counter used by the refresher/scrubber for all blocks of DRAM. The counter increments by one every eighth time the ROW ADDRESS rolls over. COL ADDRESS is readable and writable for test purposes.

  • Page 178: Table 3-15. Rom/Flash Block A Size Encoding

    The rom a siz control bits are the size of ROM/Flash for Block A. They are encoded as shown in the following table. Table 3-15. ROM/Flash Block A Size Encoding rom a siz BLOCK SIZE %000 %001 %010 %011 %100 16MB %101 32MB %110 64MB %111 Reserved http://www.motorola.com/computer/literature 3-47...

  • Page 179: Table 3-16. Rom_A_Rv And Rom_B_Rv Encoding

    Falcon ECC Memory Controller Chip Set rom_a_rv and rom_b_rv determine which if either of Blocks A and B is the source of reset vectors or any other access in the range $FFF00000 - $FFFFFFFF as shown in the table below. Table 3-16.

  • Page 180: Table 3-17. Read/Write To Rom/Flash

    No Response write 4-byte Misaligned No Response write 4-byte Aligned No Response write 4-byte Aligned Normal termination, but no write to ROM/Flash write 4-byte Aligned Normal termination, write occurs to ROM/Flash write 2,3,5,6,7, No Response 8,32-byte read Normal Termination http://www.motorola.com/computer/literature 3-49...

  • Page 181: Rom B Base/Size Register

    Falcon ECC Memory Controller Chip Set ROM B Base/Size Register Address $FEF80058 Name ROM B BASE Operation READ/WRITE READ ZERO Reset $FF4 PL ROM B BASE These control bits define the base address for ROM/Flash Block B. ROM B BASE bits 0-11 correspond to PowerPC 60x address bits 0 - 11 respectively.

  • Page 182: Table 3-18. Rom/Flash Block B Size Encoding

    ROM B BASE are enabled. When rom b en is cleared they are disabled. rom b we When rom b we is set, writes to Block B ROM/Flash are enabled. When rom b we is cleared they are disabled. Refer back to Table 3-17 for more details. http://www.motorola.com/computer/literature 3-51...

  • Page 183: Table 3-19. Rom Speed Bit Encodings

    Falcon ECC Memory Controller Chip Set ROM Speed Control Register Address $FEF80060 Name Operation READ ZERO READ ZERO READ ZERO Reset rom_a_spd0,1 determine the access timing used for ROM/Flash Block A. The encodings of these bits are as follows. Table 3-19. Rom Speed Bit Encodings rom_a/b_spd0,1 ROM Block A/B Access Time 180ns...

  • Page 184: Data Parity Error Logger Register

    Parity Error Logger control bits does affect both Falcons. This is of particular interest as regards the dpelog bit. Writing a one to the dpelog bit clears the dpelog bit for both the upper and lower Falcons. Because of this, http://www.motorola.com/computer/literature 3-53...
  • Page 185 Falcon ECC Memory Controller Chip Set software needs to check the status of both upper and lower Data Parity Error Logger, Address, and Data registers before it clears the dpelog bits. Otherwise, it could miss a logged error. dpelog is set when a parity error occurs on the Falcon’s half of the 60x data bus during any 60x data cycle.

  • Page 186: Data Parity Error Address Register

    DPE_D is the value on the Falcon’s half of the 60x data bus at the time it last logged a 60x data bus parity error. DPE_D updates only when the associated dpelog bit goes from 0 to 1. http://www.motorola.com/computer/literature 3-55...

  • Page 187: Bit Counter

    Falcon ECC Memory Controller Chip Set 32-Bit Counter Address $FEF80100 Name CTR32 Operation READ/WRITE Reset 0 PL CTR32 is a 32-bit, free-running counter that increments once per microsecond if the CLK_FREQUENCY register has been programmed properly. Notice that CTR32 is cleared by power-up and local reset. It does not exist in Revision 1 of Falcon.

  • Page 188: Power-Up Reset Status Register 2

    Data duplication is turned off for the EXTERNAL REGISTER SET so writes can be to either the upper Falcon, or to the lower Falcon. http://www.motorola.com/computer/literature 3-57...

  • Page 189: Software Considerations

    Falcon ECC Memory Controller Chip Set Note For descriptions of how these registers are used in the PowerPC series boards, refer to the Falcon-Controlled System Registers on page 1-16, especially the System External Cache Control Register (SXCCR) on page 1-20 and the CPU Control Register on page...

  • Page 190: Sizing Dram

    Initialize the Falcon control register bits to a known state as follows: 1. Clear the isa_hole bit. 2. Make sure that ram_fref and ram_spd0,ram_spd1 are correct. 3. Set CLK_FREQUENCY to match the operating frequency. 4. Clear the refdis, rwcb bits. 5. Set the derc bit. http://www.motorola.com/computer/literature 3-59...
  • Page 191 Falcon ECC Memory Controller Chip Set 6. Clear the scien, dpien, sien, and mien bits. 7. Clear the mcken bit. 8. Clear the swen and rtest0, rtest1, rtest2 bits. 9. Make sure that ROM/Flash banks A and B are not enabled to respond in the range from $00000000 to $40000000.

  • Page 192: Table 3-20. Powerpc 60X Address To Dram Address Mappings

    $00002000 $00002000 $00001000 $08000000, $02000000 $02000000 $00002000 $0A000000 $02002000 $02002000 $00003000 $04000000 $01000000 $04002000 $01001000 $06000000 $01002000 $06002000 $01003000 Table 3-20. PowerPC 60x Address to DRAM Address Mappings RA ---- Block Size 16MB 32MB 64MB 128MB 256MB 1024MB http://www.motorola.com/computer/literature 3-61...

  • Page 193: Table 3-21. Syndrome Codes Ordered By Bit In Error

    Falcon ECC Memory Controller Chip Set ECC Codes When the Falcon reports a single-bit error, software can use the syndrome that was logged by the Falcon (upper or lower depending where the error occurred) to determine which bit was in error. Table shows the syndrome for each possible single bit error.

  • Page 194: Table 3-22. Single-Bit Errors Ordered By Syndrome Code

    Table 3-22. Single-Bit Errors Ordered by Syndrome Code ckd5 ckd6 ckd7 rd45 ckd0 rd42 rd38 rd37 ckd1 rd41 rd35 rd34 rd31 rd30 rd29 ckd2 rd55 rd32 rd33 rd27 rd26 rd23 rd22 rd21 rd52 ckd3 rd54 rd51 rd47 rd48 rd24 rd25 rd19 rd18 http://www.motorola.com/computer/literature 3-63...

  • Page 195: Data Paths

    Falcon ECC Memory Controller Chip Set Table 3-22. Single-Bit Errors Ordered by Syndrome Code (Continued) rd15 rd14 rd13 rd44 ckd4 rd53 rd50 rd46 rd49 rd43 rd39 rd63 rd40 rd16 rd17 rd60 rd62 rd59 rd56 rd12 rd11 rd10 rd61 rd58 rd57 rd20 rd28 rd36...

  • Page 196: Figure 3-10. Powerpc Data To Dram Data Correspondence

    Data Paths rd63 rd32 Lower Falcon’s rd31 DRAM dl31 PowerPC Data dh31 rd63 Upper Falcon’s DRAM rd32 rd31 1909 9609 Figure 3-10. PowerPC Data to DRAM Data Correspondence http://www.motorola.com/computer/literature 3-65...

  • Page 197: Table 3-23. Powerpc Data To Dram Data Mapping

    Falcon ECC Memory Controller Chip Set Table 3-23. PowerPC Data to DRAM Data Mapping PowerPC DRAM Array A[27] A[28] Data Bits RA[1 Upper Falcon DRAM Lower Falcon DRAM Data Bits Data Bits dh[00:07] rd[00:07] dh[08:15] rd[08:15] dh[16:23] rd[16:23] dh[24:31] rd[24:31] dl[00:07] rd[00:07] dl[08:15]...
  • Page 198 Data Paths Table 3-23. PowerPC Data to DRAM Data Mapping (Continued) PowerPC DRAM Array dh[16:23] rd[48:55] dh[24:31] rd[56:63] dl[00:07] rd[32:39] dl[08:15] rd[40:47] dl[16:23] rd[48:55] dl[24:31] rd[56:63] http://www.motorola.com/computer/literature 3-67...

  • Page 199: Table 4-1. Idsel Mapping For Pci Devices

    4Programming Details Introduction This chapter contains details of several programming functions that are not tied to any specific ASIC chip. PCI Device Addressing Each PCI device has an associated address line connected via a resistor to its IDSEL pin for Configuration Space accesses. The following table shows the IDSEL assignments for the PCI devices on the MTX.

  • Page 200: Table 4-2. Pci Arbitration Assignments

    PCI arbitration is performed by the PCI-to-ISA Bridge (PIB) which supports six PCI external PCI masters. The PIB is also a PCI master for ISA DMA functions. The arbitration assignments on the MTX series are as follows: Table 4-2. PCI Arbitration Assignments...

  • Page 201: Figure 4-1. Mtx Series Interrupt Architecture

    Interrupt Handling Interrupt Handling The interrupt architecture of the MTX series SBC is shown in the following figure: INT_ Processor (8529 Pair) MCP_ RavenMPIC INT_ Processor SERR_& PERR_ PCI Interrupts MCP_ ISA Interrupts 11559.00 9609 Figure 4-1. MTX Series Interrupt Architecture...

  • Page 202: Table 4-3. Raven Mpic Interrupt Assignments

    Refer to Chapter 2, Raven PCI Host Bridge & Multi-Processor Interrupt Controller, for details on the Raven MPIC. The following table shows the interrupt assignments for the Raven MPIC on the MTX series: Table 4-3. Raven MPIC Interrupt Assignments MPIC...

  • Page 203: Interrupts

    IRQ(s) for level-sensitive mode. Note that more than one PCI interrupt can be routed to the same ISA IRQ line. The PIB can be programmed to handle the PCI interrupts if the Raven MPIC is either not present or not used. http://www.motorola.com/computer/literature...

  • Page 204: Figure 4-2. Pib Interrupt Handler Block Diagram

    Programming Details The following figure shows the interrupt structure of the PIB. Timer1/Counter0 IRQ1 PIRQ0_ IRQx IRQ3 PIRQ Route INTR Controller 1 Control Register (INT1) IRQ4 IRQ5 IRQ6 PIRQ1_ IRQx IRQ7 PIRQ Route Control Register PIRQ2_ IRQx IRQ8 PIRQ Route Control Register IRQ9 IRQ10...

  • Page 205: Table 4-4. Pib Pci/Isa Interrupt Assignments

    IRQ7 Edge High Host Parallel Port Interrupt Notes 1. Internally generated by the PIB. 2. Bit 4 of ISA Clock Divisor Register in the PIB must be set to 0 to support external keyboard interrupt (from the ISASIO device). http://www.motorola.com/computer/literature...

  • Page 206: Isa Dma Channels

    Maps, for information on the ISA DMA channels. Exceptions Sources of Reset There are five potential sources of reset on the MTX series. They are: 1. Power-On Reset 2. RESET Switch 3. Watchdog Timer Reset via the MK48T59 Timekeeper device 4.

  • Page 207: Table 4-5. Reset Sources And Devices Affected

    Processor Init Register of the Raven MPIC appropriately. Error Notification and Handling The Raven and Falcon chipset can detect certain hardware errors and can be programmed to report these errors via the Raven MPIC interrupts or Machine Check Interrupt. http://www.motorola.com/computer/literature...

  • Page 208: Table 4-6. Error Notification And Handling

    Programming Details Note The TEA* signal is not used at all by the MTX series. The following table summarizes how the hardware errors are handled by the MTX series: Table 4-6. Error Notification and Handling Cause Action Single-bit ECC Store: Write corrected data to memory...

  • Page 209: Figure 4-3. Big-Endian Mode

    (for example, AIX). Because the PowerPC processor is inherently big-endian, PCI is inherently little-endian, and the VMEbus is big-endian, things do get rather confusing. The following figures shows how the MTX series handles the endian issue in big-endian and little- endian modes: Big-Endian PROGRAM...

  • Page 210: Processor/Memory Domain

    Programming Details Little-Endian PROGRAM Little Endian Big Endian EA Modification (XOR) Falcons DRAM 60X System Bus Raven Big Endian EA Modification Little Endian PCI Local Bus Little Endian Figure 4-4. Little-Endian Mode Processor/Memory Domain The MPC604 processor can operate in both big-endian and little-endian mode.

  • Page 211: Raven's Involvement

    Since address invariance is maintained by the Raven in both little-endian and big-endian mode, there should be no endian issues for the Ethernet data. Big-endian software must still however be aware of the byte- swapping effect when accessing the registers of the PCI-Ethernet device. http://www.motorola.com/computer/literature 4-13...

  • Page 212: Rom/Flash Initialization

    Programming Details ROM/Flash Initialization There are two methods used to inject code into the Flash in Bank A: (1) In- circuit programming and (2) Loading it from the ROM/Flash Bank B. For the second method, the hardware must direct the Falcon chipset to map the FFF00000-FFFFFFFF address range to Bank B following a hard reset.

  • Page 213: Motorola Computer Group Documents

    ARelated Documentation Motorola Computer Group Documents The Motorola publications listed below are referenced in this manual. You can obtain paper or electronic copies of Motorola Computer Group publications by: Contacting your local Motorola sales office Visiting Motorola Computer Group’s World Wide Web literature site, http://www.motorola.com/computer/literature.

  • Page 214: Table A-2. Manufacturers' Documents

    Number PowerPC 603 RISC Microprocessor Technical Summary MPC603E/D MPC604E/D PowerPC 604 RISC Microprocessor Technical Summary Literature Distribution Center for Motorola Telephone: 1-800- 441-2447 FAX: (602) 994-6430 or (303) 675-2150 WebSite: http://merchant.hibbertco.com/mtrlext/ E-mail: ldcformotorola@hibbertco.com PowerPC 603 RISC Microprocessor User’s Manual MPC603EUM/D...
  • Page 215 Product Specification and User’s Manual ® (in Z8000 Family of Products Data Book) http://www.zilog.com/products/zx80dev.html#um W83C553 Enhanced System I/O Controller with PCI Arbiter (PIB) W83C553F Winbond Electronics Corporation; http://www.winbond.com.tw/product/ CL-CD1283: IEEE 1284-Compatible Parallel Interface Data Book Cirrus Logic, Inc. (or nearest Sales Office) http://www.cirrus.com http://www.motorola.com/computer/literature...

  • Page 216: Related Specifications

    Related Documentation Table A-2. Manufacturers’ Documents (Continued) Document Title and Source Publication Number PCF8584 I C Bus Controller; Philips Semiconductor; PCF8584_4.pdf http://www- Dated Oct 21 1997 us6.semiconductors.com/acrobat/datasheets/PCF8584_4.pdf Related Specifications For additional information, refer to the following table for related specifications. As an additional help, a source for the listed document is provided.

  • Page 217: Urls

    Table A-3. Related Specifications (Continued) Document Title and Source Publication Number PowerPC Microprocessor Common Hardware Reference Platform: A System Architecture (CHRP), Version 1.0 Literature Distribution Center for Motorola Telephone: 1-800- 441-2447 FAX: (602) 994-6430 or (303) 675-2150 http://merchant.hibbertco.com/mtrlext/ E-mail: ldcformotorola@hibbertco.com Morgan Kaufmann Publishers, Inc.
  • Page 218 Index Numerics block diagrams blocks A and/or B present, blocks C and D 32-Bit Counter 3-56 not present 3-22 8259 compatibility 2-50 blocks A and/or B present, blocks C and/or D 8259 interrupts present 3-23 8259 mode 2-77 bus interface (60x) 3-12 byte ordering xxii...
  • Page 219 Index data path for reads from the Falcon internal error reporting 3-17 CSRs 3-25 ERROR_ADDRESS 3-44 data path for writes to the Falcon internal ERROR_SYNDROME 3-43 CSRs 3-26 esbt 3-43 data path mapping 3-66 escb 3-42 data paths 3-64 esen 3-42 data transfers 3-13...
  • Page 220 2-76 module configuration and status registers interprocessor interrupts (IPI) 2-49 1-25 Interrupt Acknowledge Register 2-77 Motorola Computer Group documents Interrupt Acknowledge Registers 2-73 MPC bus interface interrupt delivery modes 2-51 MPC bus timer Interrupt Enable Control Bits 3-40...
  • Page 221 Index overview 2-1, power-up reset status bit 3-38 Power-Up Reset Status Register 1 3-56 Power-Up Reset Status Register 2 3-57 parity checking 3-58 PR_STAT1 bits 3-56 PC87308VUL Super I/O (ISASIO) strapping PR_STAT2 bits 3-57 1-24 PREP memory map example PCI arbitration Prescaler Adjust Register 2-25 PCI arbitration assignments...
  • Page 222 ROM/Flash B size encoding bits 3-51 PC87308VUL 1-24 ROM/Flash B Width control bit 3-50 swen 3-44 ROM/FLASH bank default 4-14 syndrome codes 3-62 ROM/Flash initialization 4-14 System Configuration Register (SYSCR) ROM/Flash speeds 3-11 1-17 rom_a_64 bit 3-47 ROM_A_BASE 3-46 http://www.motorola.com/computer/literature IN-5...
  • Page 223 Index System External Cache Control Register Z8536/Z85230 registers 1-29 (SXCCR) 1-20 system register summary 1-16 Test SRAM 3-56 tien 3-40 Timer Basecount Registers 2-66 Timer Current Count Registers 2-66 Timer Destination Registers 2-68 Timer Frequency Register 2-65 Timer Vector/Priority Registers 2-67 timers 2-50...

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