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NEC UPD98413 User Manual

NEC UPD98413 User Manual

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µPD98413
(NEASCOT-P65)
QUAD 622M ATM/POS SONET FRAMER
Preliminary User's Manual rev0.1
Document No. 2SYSM-FAD-0166
Date Published September 2001 CP (K)
NEC Corporation

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Summary of Contents for NEC UPD98413

  • Page 1 µPD98413 (NEASCOT-P65) QUAD 622M ATM/POS SONET FRAMER Preliminary User’s Manual rev0.1 Document No. 2SYSM-FAD-0166 Date Published September 2001 CP (K) NEC Corporation...
  • Page 2 The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production.
  • Page 3 SUMMARY OF CONTENTS CHAPTER 1 GENERAL................................9 CHAPTER 2 PIN FUNCTION..............................17 CHAPTER 3 FUNCTIONAL OUTLINE ..........................39 CHAPTER 4 INTERFACES ..............................113 CHAPTER 5 REGISTERS..............................159 CHAPTER 6 JTAG BOUNDARY SCAN ..........................305 PRELIMINARY NEC confidential and Proprietary...
  • Page 4 [MEMO] PRELIMINARY NEC confidential and Proprietary...

  • Page 5: Table Of Contents

    CONTENTS CHAPTER 1 GENERAL Features Ordering Information Application Block Diagram Pin Configuration Reference CHAPTER 2 PIN FUNCTION Pin Configuration Pin Function 2.2.1 Line Interface 2.2.2 ATM/POS Interface 2.2.3 Management Interface 2.2.4 Overhead Interface 2.2.5 Section and Line DCC Interface 2.2.6 Frame Pulse input pins 2.2.7 General-Purpose I/O Port...
  • Page 6 3.5.2 Drop Register Transmission/Reception of J0/J1 Trace Message 3.6.1 Transmitting Trace Message 3.6.2 Receiving Trace Message Transmitting Pseudo Frame for Testing Loopback Function CHAPTER 4 INTERFACES Line Interface ATM Interface 4.2.1 Signals 4.2.2 Cell Formats 4.2.3 Transmit operation 4.2.4 Receive operation 4.2.5 Parity 4.2.6...
  • Page 7 6.2.2 TAP (Test Access Port) Controller 6.2.3 Bypass Register 6.2.4 Boundary Scan Register Pin Function 6.3.1 JCK (JTAG Clock) Pin 6.3.2 JMS (JTAG Mode Select) Pin 6.3.3 JDI (JTAG Data Input) Pin 6.3.4 JDO (JTAG Data Output) Pin 6.3.5 JRST_B (JTAG Reset) Pin Operation Description 6.4.1 TAP Controller...
  • Page 8 [MEMO] PRELIMINARY...

  • Page 9: Chapter 1 General

    Generates and interprets payload pointer • Inserts and extracts registers of overhead bytes, ex. C2 byte • Inserts and extracts Section and Line DCCs by serial interface • Inserts and extracts whole overhead bytes by dedicated interface PRELIMINARY NEC confidential and Proprietary...

  • Page 10: Ordering Information

    Transmit valid packet and byte, Transmit abort packet, Transmit FIFO underflow packet, Receive valid packet and byte, Receive abort packet, Receive address error packet, Receive FCS error packet, Receive short packet, Receive long packet, Receive FIFO overflow drop packet Ordering Information PRELIMINARY NEC confidential and Proprietary...

  • Page 11: Application

    • Access concentrators • Add/drop multiplexers and Digital cross connects Typical Application Serial 622MHz PECL Optical Transceiver UTOPIA L3/ POS-PHY L3 Optical Transceiver ATM/POS 32-bit 104MHz Device LVTTL Optical Transceiver Optical Transceiver 32-bit LVTTL Control PRELIMINARY NEC confidential and Proprietary...

  • Page 12: Block Diagram

    Payload Type Selector TALMA RALMA RALMB TALMB RALMC TALMC TFPI ROHCK (19.44M) TOHCK (19.44M) TTOHFP RTOHFP RPOHFP TPOHFP ROHD[2] TOHD[2] ROHAV TOHAV RSDCLK(192k) TSDCLK(192k) RLDCLK(576k) TLDCLK(576k) TCS (19M) RCS (19M) REFCLK REFCLK_P/N Line Interface Port0 Tranceiver PRELIMINARY NEC confidential and Proprietary...

  • Page 13: Pin Configuration

    RSD0-3 / ROHD[0]0-3 R/W_B RLD0-3 / ROHD[1]0-3 RDY_B ROHAV0-3 INT_B RALMC0-3 Receive Alarm Pins RALMB0-3 JTAG Interface RALMA0-3 JRST_B TALMC0-3 TALMB0-3 Transmit Alarm Pins TALMA0-3 Reset pin RESET_B General I/O Ports PIO[7:0] Others Power and Ground PRELIMINARY NEC confidential and Proprietary...

  • Page 14: Reference

    Rate, and Format ”, 1995 • ANSI - T1.231 “Digital Hierarchy – Layer 1 In-Service Digital Transmission Performance Monitoring ”, October 20,1997 • PMC-1980495 “Saturn Compatible Packet over SONET Interface Specification for Physical and Link Layer Devices”, June 2000 PRELIMINARY NEC confidential and Proprietary...

  • Page 15: Chapter 2 Pin Function

    CHAPTER 2 PIN FUNCTION 2.1 Pin Configuration PRELIMINARY NEC confidential and Proprietary...
  • Page 16 CHAPTER 2 PIN FUNCTION Pin Arrangement Table PRELIMINARY NEC confidential and Proprietary...

  • Page 17: Pin Function

    The TxPLL loop filter capacitor is connected to this pin. LPFPGND Analog Loop Filter Capacitor for synthesizer PLL. (GND) The TxPLL loop filter capacitor is connected to this pin. BIASP Analog Bias pin for TxPLL Connects to analog VDD via 1.1KΩ register PRELIMINARY NEC confidential and Proprietary...
  • Page 18 Analog Loop Filter Capacitor the CDR.(GND) LPFCGND3 The CDR loop filter capacitor is connected to this pin. Each port has one pin. BIASC0-3 Analog Bias pin for CDR Connects to analog VDD via 1.1KΩ register PRELIMINARY NEC confidential and Proprietary...

  • Page 19: Atm/Pos Interface

    2 clock cycle or later after the start of output of the cell; otherwise, RXCLAV goes low. RXCLAV0 corresponds to PORT0, while RXCLAV3 corresponds to PORT3. RXADDR[1:0] Receive PHY address input. LVTTL These pins are used to input a port address for requesting data output. PRELIMINARY NEC confidential and Proprietary...
  • Page 20 PARE bit of the APIET register to report the error. An even parity can be also used depending on the setting of the MDAPIT register. Transmit address input. TXADDR[1:0] LVTTL These pins are used to input a port address for data transmission. PRELIMINARY NEC confidential and Proprietary...
  • Page 21 When RMOD[1:0] is equal to 00, RDAT[31:0] is effective. When RMOD[1:0] is equal to 01, RDAT[31:8] is effective. When RMOD[1:0] is equal to 10, RDAT[31:16] is effective. When RMOD[1:0] is equal to 11, RDAT[31:24] is effective. PRELIMINARY NEC confidential and Proprietary...
  • Page 22 Signal for controlling the port address specification using RDAT[7:0] at the start of transfer. When RSX is high and RVAL is low, a port address can be output to RDAT[7:0] to select the port used to start transfer. PRELIMINARY NEC confidential and Proprietary...
  • Page 23 Signal for inputting the odd or even parity for the data to be input to TDAT. Upon detecting a parity error, the uPD98413 reports it with an interrupt. Even if a parity error is detected, data transfer continues without being affected.
  • Page 24 Signal for controlling the port address specification using TDAT[7:0] at the start of transfer. When TSX is high and TENB_B is high, the port used to start transfer can be selected with the port address input to TDAT[7:0]. PRELIMINARY NEC confidential and Proprietary...
  • Page 25 Signal for specifying the address of the port to be polled to obtain the status of the transmission FIFO (full/not full). The transmission FIFO status for the port specified by TADR is reported by PTPA at the next clock pulse. PRELIMINARY NEC confidential and Proprietary...

  • Page 26: Management Interface

    R/W_B Read / write select signal LVTTL RDY_B Ready signal 3-state LVTTL INT_B Interrupt Output LVTTL The INT_B output is used to inform the CPU that an (unmasked) interrupt bit was set in the INT. PRELIMINARY NEC confidential and Proprietary...

  • Page 27: Overhead Interface

    TOH / POH data is input. If µ TOHAV is high, the PD98413 inputs the data on TOHD in that cycle and the next three cycles; when TOHAV is low, µ PD98413 does not input the data. PRELIMINARY NEC confidential and Proprietary...
  • Page 28 This signal indicates that valid receive TOH data is output to ROHD. In the clock cycle in which valid data is output to ROHD, ROHAV goes high. In the clock cycle in which valid data is not output, ROHAV goes low. PRELIMINARY NEC confidential and Proprietary...

  • Page 29: Section And Line Dcc Interface

    RLDCLK0 corresponds to PORT0, while RLDCLK 3 corresponds to PORT3. RLD0-3 Receive line DCC (RLD) signals contains the serial line data communications channel (D4-D12) extract from the LVTTL incoming stream. RLD0 corresponds to PORT0, while RLD3 corresponds to PORT3. PRELIMINARY NEC confidential and Proprietary...

  • Page 30: Frame Pulse Input Pins

    General-purpose output The settings of the bits of the internal GPOUT register are output to these pins as signal levels. These pins can be used to control external peripheral devices. PRELIMINARY NEC confidential and Proprietary...

  • Page 31: Alarm Signal Input / Output

    Enhanced PRDI mode - PERDI Server defect (G1 bit5- 7 : 101) 101: PERDI Connectivity defect (G1 bit5-7 : 110) 110: PERDI Payload defect (G1 bit5-7 : 010) 111: Reserved TALMx 0 corresponds to PORT0, while TALMx 3 corresponds to PORT3. PRELIMINARY NEC confidential and Proprietary...

  • Page 32: Jtag Boundary Scan

    2.2.11 Power and Grounding Pins Pin Name Serial No. Address No. Function − Power supply pins − Ground pins 2.2.12 Others Pin Name Serial No. Address No. I/O Level Function − Internal circuit connection test pins. PRELIMINARY NEC confidential and Proprietary...

  • Page 33: Handling Unused Pins

    CHAPTER 2 PIN FUNCTION 2.2.13 Handling Unused Pins PRELIMINARY NEC confidential and Proprietary...

  • Page 34: Initial States Of Each Pin

    CHAPTER 2 PIN FUNCTION 2.2.14 Initial States of Each Pin PRELIMINARY NEC confidential and Proprietary...
  • Page 35 [MEMO] PRELIMINARY NEC confidential and Proprietary...
  • Page 36 In this document, the following two descriptions are also used to indicate the same overhead byte in the SDH/SONET frame. Description <1> 1st H1 2nd H1 3rd H1 47th H1 48th H1 1st H1 2nd H1 Description <2> H1#1 H1#2 H1#3 H1#47 H1#48 H1#1 H1#2 PRELIMINARY NEC confidential and Proprietary...

  • Page 37: Chapter 3 Functional Outline

    Line interface card Figure 3-2. Transmit/Receive Data Flow of µ µ µ µ PD98413 622.08 STS-12c/STM4 frame µPD98413 Cell Port 0 framer ATM cell / Packet Port 1 framer Overhead Port 2 framer Cell Port 3 framer PRELIMINARY NEC confidential and Proprietary...
  • Page 38 ATM cell/POS packet overhead … … … … (LOH) Fixed … … … … Fixed Stuff Payload … stuff … 3byte Transport overhead (TOH) 36 bytes Path overhead (POH) 1 byte STS-12c SPE 1,043 bytes PRELIMINARY NEC confidential and Proprietary...
  • Page 39 : Section user channel : Growth : Multiframe indicator D1-D3 : Section data communication : Growth Z3-Z5 : Growth channel H1, H2 : Pointer : STS-N line REI : Pointer action byte : Order wire PRELIMINARY NEC confidential and Proprietary...

  • Page 40: Sonet Overhead Processing

    FFH by using the UUBM bit of the MDSOHT and MDLOHT registers. <1> Unused byte area (area marked in Figure 3-5) <2> H3 byte (Negative Stuff byte) <3> Z1 and Z2 bytes (except the 1st Z2 byte) PRELIMINARY NEC confidential and Proprietary...
  • Page 41 Because Frequency Justification (stuff operation) is not requested at the transmission side, payload data is not set in the H3 byte that is used as Negative Stuff byte. Instead, the H3 byte is set to all zeros and transmitted. PRELIMINARY NEC confidential and Proprietary...
  • Page 42 (J1) of SPE. The offset value increments by 12 bytes as shown in Figure 3-8. If the pointer value is 0, for example, it indicates that SPE starts from the byte position immediately after the H3 byte. If the pointer value is 522 (20AH), SPE starts from the position immediately after the 11th Z0. PRELIMINARY NEC confidential and Proprietary...
  • Page 43 High OH insert interface Internal processing of µPD98413 J0, J1 byte • BIP, REI processing trace message OH insert register Section and Line DCC • Pointer processing transmission command insert interface • Transmission of alarm PRELIMINARY NEC confidential and Proprietary...
  • Page 44 36 bytes of "A1, A2, J0 and Z0". Polynomial G (X) = 1 + X The user can select a scramble stop mode for the purpose of testing. The scramble stop mode is selected by the FSCM bit of the MDSOHT register. PRELIMINARY NEC confidential and Proprietary...
  • Page 45 For details of the pseudo error frame transmission function, see Section 3.7 . • Types of pseudo frames generated <1> LOS <2> OOF/LOF <3> LOP <4> OCD/LCD <5> B1 error <6> B2 error <7> B3 error <8> Line REI <9> Path REI PRELIMINARY NEC confidential and Proprietary...

  • Page 46: Reception Function

    OOF and LOF statuses the same. µ s, the µ PD98413 enters the Loss Of Signal If the levels of the signals input to RDIT, RDIC do not change for 25 (LOS) status. PRELIMINARY NEC confidential and Proprietary...
  • Page 47 Z0 (11)" is descrambled. Polynomial G (X) = 1 + X An option mode that disables descrambling of a frame is provided for testing purposes. This mode is set by using the FSCM Bit of the MDSOHR register. PRELIMINARY NEC confidential and Proprietary...
  • Page 48 Indicate the type of SPE. Pointer: Indicates the position of first byte J1 of POH and requests Frequency Justification (stuff operation). I (Increment bit): Requests Positive Justification operation. D (Decrement bit): Requests Negative Justification operation. Concatenation indication: Indicates concatenation. PRELIMINARY NEC confidential and Proprietary...
  • Page 49 An abnormality occurs in an upstream device or transmission path. Data cannot be received normally. LOP status: The receive pointer value is not normal. Data cannot be received normally. Figure 3-10. Pointer Status Transition NORM PRELIMINARY NEC confidential and Proprietary...
  • Page 50 MDPTRR register. <4> Conflict condition • If the Frequency Justification operation is interpreted but the actual operation involves changing the pointer value to a new value, the pointer value is changed after the Frequency Justification operation. PRELIMINARY NEC confidential and Proprietary...
  • Page 51 <1> N: In the default status, the number of times of reception is nine, but this can be changed to eight or ten times by using the LOPN[1:0] bits of the MDPTRR register. PRELIMINARY NEC confidential and Proprietary...
  • Page 52 Table 3-7 shows the status transition condition of pointer processing of H1#1 and H2#1, H1#2 and H2#2 to H1#12 and H2#12. Figure 3-11 shows the status transition. Figure 3-11. Status Transition of Processing (Bellcore MODE) <8> <9> <7> NORM <2> <5> <4> <1> <4> <5> PRELIMINARY NEC confidential and Proprietary...
  • Page 53 Concatenation Interpretation. (but transition<8> take precedence over transition <5>) Detect N×Inv_point of H1#1 and H2#1. (but transition<8> take precedence over transition <5>) <7><8><9> The transition from NORM to NORM do not represent changes of state but imply offset change. PRELIMINARY NEC confidential and Proprietary...
  • Page 54 SS bits, and pointer values extracted from each pair of bytes are classified into the following indication and interpreted. Figure 3-12. Status Transition of Concatenation Indication CONC <4> <2> <3> <1> <3> LOPC AISC <4> H1#2 and H2#2 H1#3 and H2#3 H1#4 and H2#4 H1#12 and H2#12 PRELIMINARY NEC confidential and Proprietary...
  • Page 55 LOP or LOPC or NORM or CONC in any of H1#1 and H2#1 to H1#12 and H2#12. However, the transition <a> takes precedence. → <d> NORM LOP or LOPC or AIS or AISC in any of H1#1 and H2#1 to H1#12 and H2#12. However, the transition <b> takes precedence. PRELIMINARY NEC confidential and Proprietary...
  • Page 56 782 ….. 782 781 ….. 781 H1 ..H1 H2 ..H2 H3 ..H3 0 …..0 1 ….. 86 ….. 86 87 …..87 STS-12c SPE Fixed stuff byte 521 ….. 521 435 ….. 435 PRELIMINARY NEC confidential and Proprietary...
  • Page 57 OAM (Operation, Administration and Maintenance) information is provided. • Detection of failure and alarm • Detection of cause of line quality degradation • Performance monitoring counter • Monitoring bit error rate For details, see Section 3.4 . PRELIMINARY NEC confidential and Proprietary...

  • Page 58: Atm Function

    Network node interface (NNI) Header Payload data Payload data 48 bytes 48 bytes GFC: Generic flow control PTI: Payload type identifier VPI: Virtual path identifier CLP: Cell loss priority VCI: Virtual channel identifier HEC: Header error control PRELIMINARY NEC confidential and Proprietary...

  • Page 59: Transmit Atm Function

    And if HEC generation is disabled and HEC is inserted from ATM device, the HEC field of ATM Cell is inserted the original value that inserted from ATM device. Polynomial G (X) = X + X + 1 PRELIMINARY NEC confidential and Proprietary...
  • Page 60 48-byte payload of the ATM cell. Polynomial G (X) = X The user can select a scramble stop mode for the purpose of testing. The scramble stop mode is set by the CSCM bit of MDATMT register. PRELIMINARY NEC confidential and Proprietary...

  • Page 61: Receive Atm Function

    Figure 3-17. Cell Synchronization Status Transition Hunting status (HUNT) No HEC error HEC error α times in row HEC error Preceding synchronization status (PRESYNC) Cell synchronization status HEC without error (SYNC) δ times in row PRELIMINARY NEC confidential and Proprietary...
  • Page 62 If the LCDDT bit of the MDATMR register If the LCDDT bit of the MDATMR register is 0, the LCD status is detected at the is 0, the LCD status is cleared at the same same time as OCD. time as OCD. PRELIMINARY NEC confidential and Proprietary...
  • Page 63 Table 3-11. HEC Error Control Mode Execution of 1-bit error correction MDATMR Register of header HECCM Bit None Correction executed (default) ε Number of stages ( ) for changing MDATMR Register mode from detection to correction HECDC[1:0] Bits 1 (default) PRELIMINARY NEC confidential and Proprietary...
  • Page 64 FIFO is full, a receive FIFO overflow error occurs and that cell is dropped. The occurrence of the receive FIFO overflow error can be used as an interrupt cause. PRELIMINARY NEC confidential and Proprietary...

  • Page 65: Pos Functions

    POS interface. The mapping of POS packets into a SONET payload and the POS packet format are shown below. Figure 3-20. Mapping of POS Packets POS packet POS packet POS packet Payload Fixed stuff PRELIMINARY NEC confidential and Proprietary...

  • Page 66: Transmission Pos Functions

    If the address and control byte generation function is enabled, FCS operation is executed on the entire packet data, including the address and control bytes. The FCS generation function is optional and it may be disabled by the FCSM bit of the MDPOST register. PRELIMINARY NEC confidential and Proprietary...
  • Page 67 In PPP over SONET, the values of the C2 and H4 bytes of the SONET overhead bytes are defined. Set the transmission C2 and H4 byte registers to the following values: C2 byte: 16h when scrambling is used CFh when scrambling is not used H4 byte: 00h (Default value of register) PRELIMINARY NEC confidential and Proprietary...
  • Page 68 (the TSOP of the next packet is asserted before TEOP is asserted), the µ PD98413 indicates the error and interrupt. TERR signal is asserted If the TERR signal is asserted during packet transmission, the µ PD98413 inserts 7Dh and 7Eh and sends the data as an abort packet. PRELIMINARY NEC confidential and Proprietary...
  • Page 69 FIFO underflow and TERR is asserted. See the description above for details of the transmission of an abort packet. Transmit FIFO underflow packet counter The µ PD98413 increments the transmit FIFO underflow packet counter when a transmit FIFO underflow occurs during packet transmission. PRELIMINARY NEC confidential and Proprietary...
  • Page 70 Flag sequence Terminal of Partial paket Flag sequence Flag sequence Name Value Flag sequence Terminal of Partial paket 7Dh-xxh (xx is the value, which set by the STPN[7:0] bits of the HPTNT register.) PRELIMINARY NEC confidential and Proprietary...

  • Page 71: Reception Pos Functions

    Remark If 7D-7Eh bytes are detected in a POS packet, the µ PD98413 does not perform byte destuffing. That packet is processed as an abort packet. The µ PD98413 also performs byte destuffing if the byte following the control escape (7Dh) is not 5Dh, 5Eh, or 7Eh. PRELIMINARY NEC confidential and Proprietary...
  • Page 72 The received abort packet, which is stripped an abort sequence (7D-7E), is output from the POS interface. At the end of the packet, the RERR pin is asserted for notification. PRELIMINARY NEC confidential and Proprietary...
  • Page 73 POS packet) and checks it. If the value in the Address field of the packet is not FFh or the control field is not 03h, the packet is handled as an address error packet, and the address error counter is incremented. Receive FCS error counter Upon detecting an FCS error, the µ PD98413 increments the FCS error counter. PRELIMINARY NEC confidential and Proprietary...
  • Page 74 The µ PD98413 allows you to set the maximum receive packet size (settable in an appropriate register, programmable). Upon receiving a packet whose size exceeds the maximum, the µ PD98413 increments the long size packet counter. PRELIMINARY NEC confidential and Proprietary...
  • Page 75 Flag sequence Extructing Packet Address Control Partial packet Partial packet Partial packet Name Value Flag sequence Terminal of Partial paket 7Dh-xxh (xx is the value, which set by the STPN[7:0] bits of the HPTNR register.) PRELIMINARY NEC confidential and Proprietary...

  • Page 76: Oam Function

    Can be set Can be set Line RDI simultaneously. simultaneously. Path RDI Line AIS Path AIS Can be set Can be set simultaneously. simultaneously Line AIS Can be set Line RDI Can be set simultaneously. simultaneously. PRELIMINARY NEC confidential and Proprietary...
  • Page 77 This frame has "1" in all the H1, H2, and H3 bytes of the AU pointer of the OH byte of a transmit frame, and all the bits in the SPE area (POH and payload) before frame scramble. PRELIMINARY NEC confidential and Proprietary...
  • Page 78 <3> Drive the TALM pins to the One-bit Path RDI code. While these pins are set to the One-bit Path RDI code, the One-bit Path RDI frame is transmitted. • • • • One-bit Path RDI frame This frame has "1" in bit 5 of the G1 byte of the OH byte. PRELIMINARY NEC confidential and Proprietary...
  • Page 79 No RDI-P defect ERDI-P Server defect ERDI-P Connectivity defect ERDI-P Payload defect • • • • Enhanced Path RDI frame This frame has the above value in bit 5-7 of the G1 byte of the OH byte. PRELIMINARY NEC confidential and Proprietary...

  • Page 80: Detection Of Alarm And Failure

    * T = 3 ms or 0 ms. This can be selected by using the LOFDT bit of the MDSOHR register. In the default mode, T = 3 ms. When T = 0 ms, the detection/clearing condition is the same as that of OOF. PRELIMINARY NEC confidential and Proprietary...
  • Page 81 See (3) in Section 3.1.2. Path AIS (Path Alarm Indication Signal) Path alarm indication signal. Detects occurrence of Path AIS in unit of transmission source (upstream). Detection: See (3) in Section 3.1.2. Termination: See (3) in Section 3.1.2. PRELIMINARY NEC confidential and Proprietary...
  • Page 82 Path TIM (Path Trace Identifier Mismatch) Path trace identifier mismatch. Detection: See Section 3.6. Termination: See Section 3.6. Path TIU (Path Trace Identifier Unstable) Path trace identifier unstable. Detection: See Section 3.6. Termination: See Section 3.6. PRELIMINARY NEC confidential and Proprietary...
  • Page 83 The changes in the input level of the CD pin can be included in the LOS detection condition by setting the CDO bit of the MDSOHR register. CD pin = Low: LOS status High: Normal status (Notice that the pin input level is opposite to the logic of the bit of the register.) PRELIMINARY NEC confidential and Proprietary...

  • Page 84: Alarm Management

    When LOS and LOF is detected PSBF When LOS, LOF or Line AIS is detected. Path RDI When LOS, LOF, Line AIS, LOP or Path AIS is detected. Path PLM Path UNEQ Path TIM Path TIU PRELIMINARY NEC confidential and Proprietary...
  • Page 85 Receive HEC error correct cell counter Receive HEC error drop cell counter Receive valid packet counter When LOS, LOF, Line AIS, LOP or Path AIS is detected. Receive abort packet counter Receive address error packet counter PRELIMINARY NEC confidential and Proprietary...

  • Page 86: Aps (Automatic Protection Switching)

    K1 byte is missing three times in a row in 12 continuous frames, the µ PD98413 indicates this status as the PSBF. The PSBF status is terminated if a frame having the same K1 byte has been received three times in a row. If µ PD98413 detecting Line AIS, status of PSBF is not change. PRELIMINARY NEC confidential and Proprietary...
  • Page 87 (setting by the UADR bit of the PTADRT register) protection working port (Port3) (Port2) port (Port 0) (Port1) Port3 Port2 Port1 Port0 Transmit Transmit Transmit Transmit FIFO FIFO FIFO FIFO same cell/packet UTOPIA/POS-PHY Interface PRELIMINARY NEC confidential and Proprietary...
  • Page 88 (setting by the UADR bit of the PTADRR register) protection working port (Port3) (Port2) port (Port 0) (Port1) Port3 Port2 Port1 Port0 Receive Receive Receive Receive FIFO FIFO FIFO FIFO UTOPIA/POS-PHY Interface PRELIMINARY NEC confidential and Proprietary...

  • Page 89: Monitoring Signal Label Byte

    The default value of the C2EX field is 13H. When the Path PLM is detected, the µ PD98413 indicates this error by the interrupt. If the µ PD98413 is detecting LOS, LOF, LOP, L-AIS or P-AIS, the Path PLM is not detected. PRELIMINARY NEC confidential and Proprietary...
  • Page 90 Path UNEQ, Path PLM Path UNEQ, Path PLM None (Matched) Path PLM None (Matched) None(Matched) Path PLM Path PLM Note: XXh = anything except 00h or 01h YYh = anything except 00h or 01h, and not equal XXh. PRELIMINARY NEC confidential and Proprietary...

  • Page 91: Monitoring Line Quality (Performance Monitoring)

    1 frame AU pointer 9 rows Before scramble 6 rows 1 frame AU pointer Before scramble 9 rows B2 × × × × 12 : BIP operation range B2 × 12: BIP operation result of preceding PRELIMINARY NEC confidential and Proprietary...
  • Page 92 Whether Path BIP-8 error occurs is reported to a unit in the upstream. When the µ PD98413 detects a B3 error in the receive frame, it automatically stores the erroneous interleaved bit blocks to the G1 byte (bits 1 to 4) of the transmit frame. PRELIMINARY NEC confidential and Proprietary...
  • Page 93 8 is received. 0 and 9 through 15 values are no error. The value stored to this area is the number of interleaved bit blocks in which an error has been detected as a result of path layer BIP-8 operation at the transmission destination (downstream). PRELIMINARY NEC confidential and Proprietary...
  • Page 94 Number of short packets due to short size packet error Note: The HEC drop cell counter and HEC Correct counter operate differently depending on the mode setting of HEC error control by the MDATMR registers. PRELIMINARY NEC confidential and Proprietary...
  • Page 95 CAMPR register. 4. If the counter will be overflow, the counter start counting from 0 again, and the corresponding bit of the registers is set to 1 to report the overflow to the CPU. PRELIMINARY NEC confidential and Proprietary...
  • Page 96 Default Values of the Parameters Parameter Number of frames (24 bits) 000 H 000 H Number of errors detected (12 bits) 000 H 000 H Number of consecutive frames (8 bits) 00 H 00 H PRELIMINARY NEC confidential and Proprietary...
  • Page 97 × : LD or more errors are detected in the ND frame. ∆ : Less than LT errors are detected in the NT frame. N frame Ο × × × × ∆ ∆ ∆ ∆ × × Three consecutive frames Four consecutive frames Degradation 1 indication PRELIMINARY NEC confidential and Proprietary...

  • Page 98: Overhead Insert/Drop Function

    1st Z2 bit6-7 Z2FDR 1st Z2 bit7-8 Z2FMR 1st H1 SS bit MDLOHT 00(b) J1C2T 16(H) J1C2T 00(H) G1F2H4T 00(H) G1F2H4R G1F2H4T 00(H) G1F2H4R G1F2H4T 00(H) G1F2H4R Z345T 00(H) Z345R Z345T 00(H) Z345R Z345T 00(H) Z345R PRELIMINARY NEC confidential and Proprietary...

  • Page 99: Insert Register

    This register is updated if the values of the bit7-8 of 1st Z2 are the same in 12 frames received continuously after When this register is updated, the µ PD98413 the different value from that received previously is detected. indicates it to the Z2M bit of the DSLER register and interrupt. PRELIMINARY NEC confidential and Proprietary...

  • Page 100: Transmission/Reception Of J0/J1 Trace Message

    Set the offset address of the trace message buffer TMBT register Buffer BDAT bit BDAT bit Access to Accepted buffer, Access register TMDT register Transmit J0STAT bit J1STAT bit Start to transmit new trace massage. command CMTMT register PRELIMINARY NEC confidential and Proprietary...
  • Page 101 If transmit next new trace message, overwrite setting buffer and then enable the transmission command. Note: after enable the transmission command, the transmission command register is not return to 0. Therefore, if transmit next trace message, write 0 to the register, and then write 1 to the register. PRELIMINARY NEC confidential and Proprietary...
  • Page 102 00H to 01H of for 00H to 01H of for 00H to 01H of J1 Expected Buffer. J1 Expected Buffer. J1 Expected Buffer. J1 Expected Buffer. J0 Expected Buffer. J0 Expected Buffer. J0 Expected Buffer. J0 Expected Buffer. PRELIMINARY NEC confidential and Proprietary...

  • Page 103: Receiving Trace Message

    Which to Access is setting by buffer select register register (TMBT). TMDR register J0PTN bit J1PTN bit Set the synchronous pattern of J0/J1 massage detecting pattern J0M bit J1M bit Set the mask value of the synchronous pattern. setting J0PTN J1PTN register PRELIMINARY NEC confidential and Proprietary...
  • Page 104 (pointer = 00H). If the synchronization pattern is specified as the end byte of the message, the data is rearranged so that the synchronization pattern is at the end of the message. PRELIMINARY NEC confidential and Proprietary...
  • Page 105 Each time the CPU has accessed the access register, the µ PD98413 automatically increments the pointer of the buffer. Upon the completion of reading from the highest address of the pointer, incremented each time a read is performed, the pointer is automatically returned to 0. PRELIMINARY NEC confidential and Proprietary...
  • Page 106 00H to 03H of for 00H to 03H of for 00H to 03H of J1 Expected Buffer. J1 Expected Buffer. J1 Expected Buffer. J1 Expected Buffer. J0 Expected Buffer. J0 Expected Buffer. J0 Expected Buffer. J0 Expected Buffer. PRELIMINARY NEC confidential and Proprietary...
  • Page 107 00H to 01H of for 00H to 01H of for 00H to 01H of J1 Expected Buffer. J1 Expected Buffer. J1 Expected Buffer. J1 Expected Buffer. J0 Expected Buffer. J0 Expected Buffer. J0 Expected Buffer. J0 Expected Buffer. PRELIMINARY NEC confidential and Proprietary...
  • Page 108 Termination: If the mPD98413 received same J1 massage three or five times (set to the PTIMDT bit of the MDPOHR register) continuously, and that message equal to expected massage. When the µ PD98413 detects the Path TIM, the status is indicated as J1 Path TIM in the DPPER register. PRELIMINARY NEC confidential and Proprietary...

  • Page 109: Transmitting Pseudo Frame For Testing

    Line REI PLREI frame register for transmission. PEPOH register Sets bits 1 to 4 of G1 byte to the value set in the PG1[3:0] bits of the Path REI PPREI frame PEPOH register for transmission. PRELIMINARY NEC confidential and Proprietary...

  • Page 110: Loopback Function

    In this mode, the data input from the reception side of the line interface is returned at the µ PD98413 internal and output from the transmission side of the line interface. Figure 3-35. Line Loopback Tx PLL TDOT0/ MUX 0 TDOC0 Lock state RDIT0/ RDIC0 DEMUX 0 SDT0 PRELIMINARY NEC confidential and Proprietary...

  • Page 111: Chapter 4 Interfaces

    Figure 4-1. Overview of µ µ µ µ PD98413 line interface block BIASP LPFP LPFPGND RFCKTTL TxPLL RFCKPLT/ RFCKPLC TDOT0/ MUX 0 TDOC0 78MHz FRAMER0 Lock state RDIT0/ DEMUX 0 RDIC0 78MHz CDVREF PORT 0 LPFC0 BIASC0 LPFCGND0 PRELIMINARY NEC confidential and Proprietary...
  • Page 112 CDR from the receive data as the transmit clock. This setting is made for each port and does not affect the transmit clock setting of the other ports. Figure 4-2. Loop timing mode TDOT0/ TDOC0 MUX 0 Lock state RDIT0/ DEMUX 0 RDIC0 BIASC0 LPFC0 LPFCGND0 PRELIMINARY NEC confidential and Proprietary...
  • Page 113 CDR from the receive data as the transmit clock. In that case, if CDR enter OOL status, the transmit clock is forcibly switched to the clock generated by TxPLL. The low level of CD signal can be used as a condition for LOS detection. PRELIMINARY NEC confidential and Proprietary...
  • Page 114 CHAPTER 4 INTERFACES (7) Connection example PRELIMINARY NEC confidential and Proprietary...

  • Page 115: Atm Interface

    An example of connecting the ATM interface is shown below. Figure 4-3. Example of Connecting the ATM Interface RXCLK RXENB_B RXDATA[31:0] RXPRTY RXSOC RXCLAV0-3 uPD98413 ATM device RXADDR[1:0] TXCLK TXENB_B TXDATA[31:0] TXPRTY TXSOC TXCLAV0-3 TXADDR[1:0] PRELIMINARY NEC confidential and Proprietary...
  • Page 116 TXADDR[1:0] is used to select the port for which the transmit data is to be destined. The address is used in both the direct status indication mode and the status-polling mode. The following addresses show the corresponding ports. 0: port0, 1: port1, 2: port2, 3: port3   PRELIMINARY NEC confidential and Proprietary...
  • Page 117 RXADDR is used to select the port from which the receive data is to be read. The address is used in both the direct status indication mode and the status polling mode. The following addresses show the corresponding ports. 0: port0, 1: port1, 2: port2, 3: port3   PRELIMINARY NEC confidential and Proprietary...

  • Page 118: Cell Formats

    Received HEC is dropped within the µPD98413 and a cell is output as 52- are combined and inserted into the second word position of a cell and the byte (13-word) data. cell is output as 56-byte (14-word) data. PRELIMINARY NEC confidential and Proprietary...

  • Page 119: Transmit Operation

    TXENB_B is asserted. This signal will be decoded by the µPD98413 and the specified port will be ready to receive cell data from the ATM device as soon as the TXENB_B is asserted. The following figure shows an example of the transmit timing in the direct status indication. PRELIMINARY NEC confidential and Proprietary...
  • Page 120 TXSOC is asserted to indicate the start of cell. This example is illustrated below. Figure 4-6. Back-to-back Cell Transmission (Direct Status Indication) TXCLK TXADDR[1:0] PORT0 TXCLAV0 TXCLAV1 TXCLAV2 TXCLAV3 TXENB_B TXDATA[31:0] TXPRTY TXSOC X : Invalid PRELIMINARY NEC confidential and Proprietary...
  • Page 121 µPD98413 port by leaving the TXENB_B asserted during the next to the last cycle of the cell transfer. The second cell is transferred immediately after the previous one and the TXSOC is asserted to indicate the start of cell. This example is illustrated below. PRELIMINARY NEC confidential and Proprietary...

  • Page 122: Receive Operation

    The decode-response timing between the RXENB_B and the RXDATA[31:0] is therefore two clock cycles Figure 4-9. Receive Timing (Direct Status Indication) PRELIMINARY NEC confidential and Proprietary...
  • Page 123 CHAPTER 4 INTERFACES RXCLK RXADDR[1:0] PORT0 PORT1 RXCLAV0 RXCLAV1 RXCLAV2 RXCLAV3 RXENB_B RXDATA[31:0] RXPRTY RXSOC X : Invalid PRELIMINARY NEC confidential and Proprietary...
  • Page 124 The decode-response timing between the RXENB_B and the RXDATA[31:0] is therefore two clock cycles The following figure shows an example of the transmit timing in the status polling. PRELIMINARY NEC confidential and Proprietary...
  • Page 125 RXSOC is asserted to indicate the start of cell. This example is illustrated below. Figure 4-12. Back-to-back Cell Reception (Status Polling) RXCLK RXADDR[1:0] PORT3 PORT0 PORT1 PORT2 PORT3 PORT0 RXCLAV0 PORT3 PORT0 PORT1 PORT0 RXENB_B RXDATA[31:0] RXPRTY RXSOC X : Invalid PRELIMINARY NEC confidential and Proprietary...

  • Page 126: Parity

    µPD98413 indicate the error by the APIET register. - TXENB_B and TSOC error If the µPD98413 detect that TXENB_B is deasserted or TSOC is asserted while a cell transfer, the µPD98413 indicate the error by the APIET register. PRELIMINARY NEC confidential and Proprietary...
  • Page 127 If the µPD98413 is detect that RXENB_B is deasserted or RXSOC is asserted while a cell transfer, the µPD98413 indicate the error by the APIER register. - Port select error If the µPD98413 select the port although the corresponding RXCLAV is low, the µPD98413 indicate the error by the APIER register. PRELIMINARY NEC confidential and Proprietary...

  • Page 128: Pos Interface

    An example of connecting the POS interface is shown below. Figure 4-13. Example of Connecting the POS Interface RFCLK RENB_B RXDAT[31:0] RMOD[1:0] RPRTY RVAL uPD98413 POS device RSOP REOP RERR TFCLK TENB_B TDAT[31:0] TMOD[1:0] TPRTY TSOP TEOP TERR DTPA0/PTPA DTPA1-3 STPA TADR[1:0] PRELIMINARY NEC confidential and Proprietary...
  • Page 129 TDAT[31:0] are specified by TMOD[1:0] below. 00: TDAT[31:0] is valid. 01: TDAT[31:8] is valid. 10: TDAT[31:16] is valid. 11: TDAT[31:24] is valid. TMOD[1:0] is considered valid only when TENB_B is asserted. PRELIMINARY NEC confidential and Proprietary...
  • Page 130 When the µPD98413 samples TADR[1:0] on the rising edge of TFCLK, the PTPA signal is updated with the status of the port specified by TADR[1:0] on the following rising edge of TFCLK. The following addresses show the corresponding ports. 0: port0, 1: port1, 2: port2, 3: port3 PRELIMINARY NEC confidential and Proprietary...
  • Page 131 00: RDAT[31:0] is valid. 01: RDAT[31:8] is valid. 10: RDAT[31:16] is valid. 11: RDAT[31:24] is valid. RMOD[1:0] is considered valid only when RVAL is asserted. RMOD[1:0] is 0, except during the last word transfer of a packet. PRELIMINARY NEC confidential and Proprietary...

  • Page 132: Packet Formats

    µPD98413 outputs the following addresses for the corresponding ports. 0: port0, 1: port1, 2: port2, 3: port3 4.3.2 Packet Formats The format of the packet transferred via the POS interface in the following figure. Figure 4-14. Packet Format Example: 62-byte packet 16 words PRELIMINARY NEC confidential and Proprietary...

  • Page 133: Transmit Operation

    In the direct status indication mode, the PTPA and TADR[1:0] signals are not used. Figure 4-15. Transmit Timing (Direct Status Indication) TFCLK TENB_B TSOP TEOP TMOD[1:0] TERR TDAT[31:0] 0000 B1-B4 B5-B8 B41-B44 B45-B48 B49-B52 B53-B56 0001 B1-B4 B5-B8 TPRTY STPA DTPA0 DTPA1 DTPA2 DTPA3 X : Invalid PRELIMINARY NEC confidential and Proprietary...

  • Page 134: Receive Operation

    Figure is an example of the receive timing. The µPD98413 informs the POS device of the selected port by asserting RSX with the port address on the RDAT bus. Figure 4-17. Receive Timing RFCLK RENB_B RSOP REOP RERR RMOD[1:0] RDAT[31:0] A(0) A(2) RPRTY RVAL PRELIMINARY NEC confidential and Proprietary...
  • Page 135 CHAPTER 4 INTERFACES PRELIMINARY NEC confidential and Proprietary...
  • Page 136 Figure 4-19 In-band address inserted receive operation RFCLK RENB RSOP REOP RERR RMOD[1:0] RDAT[31:0] A(0) A(0) A(0) RPRTY RVAL Idol Burst transfer size Clock Must be inserted In-band Address, however the port is not chenged PRELIMINARY NEC confidential and Proprietary...

  • Page 137: Parity

    FIFO. If a parity error is detected, the µPD98413 indicate the error by the APIET register. - Packet discard error If the µPD98413 detects packet discard, because TPA is ignore and transmit FIFO overflow occurs, the µPD98413 indicate the error by the APIET register. PRELIMINARY NEC confidential and Proprietary...
  • Page 138 The µPD98413 is generate the parity when receive packet is stored in the receive FIFO, and check the parity when receive packet is take out from the receive FIFO. If a parity error is detected, the µPD98413 indicate the error by the APIER register. PRELIMINARY NEC confidential and Proprietary...

  • Page 139: Overhead Insert/Extract Interfaces And Section/Line Dcc Insert/Extract Interface

    RSDCLK / RTOHFP Interface Interface TPOHFP / TLDCLK RLDCLK / RPOHFP TOHD[0] / RSD RSD / ROHD[0] Section / Section / Line DCC Line DCC TOHD[1] / RLD RLD / ROHD[1] extract insert TOHAV ROHAV Interface Interface PRELIMINARY NEC confidential and Proprietary...

  • Page 140: Oh Insert Interface

    Bit2 Bit4 Bit6 Bit8 Bit2 Bit4 Bit6 Bit8 Bit2 Bit4 Bit6 Bit8 Bit2 Bit4 Bit6 Bit8 TOHD[0]( 1st A1 2nd A1 IDLE 144 Clock (36×4) 4 Clock 122 Clock 270 Clock peripheral device Don’t care uPD98413 sampling sampling PRELIMINARY NEC confidential and Proprietary...
  • Page 141 µ J0, J1 byte Internal processing of PD98413 OH insert register OH insert interface • BIP, REI processing trace message • Pointer processing transmission command Section and Line DCC • Transmission of alarm insert interface PRELIMINARY NEC confidential and Proprietary...
  • Page 142 [2:0] bits of the CMALM register is set, alarm transmission takes precedence, and this bit is set to 1. When the µPD98413 transmits alarm Line AIS, alarm transmission takes All bytes of LOH and POH precedence, and all the bits are set to 1 for transmission. PRELIMINARY NEC confidential and Proprietary...

  • Page 143: Oh Extract Interfaces

    POH data is extracted, ROHAV is held high. If an alarm or fault such as LOS, LOF, OOF, and Line AIS is detected in the reception line, the µPD98413 drives ROHAV low to indicate that the output data on ROHD [1:0] is invalid. PRELIMINARY NEC confidential and Proprietary...

  • Page 144: Transmit Section And Line Dcc Insert Interface

    9×RLDCLK PRELIMINARY NEC confidential and Proprietary...

  • Page 145: Frame Pulse Input Pins

    µPD98413 starts transmit frame after fixed delay. Therefore, please avoid the usage every frame input. TFPI is sampled on the own rising edge. TFPI must be tied low if not use this pin. TFPI is enabled by the setting of the TFPE bit of the MDPT register. PRELIMINARY NEC confidential and Proprietary...

  • Page 146: General-Purpose Input And Output Ports

    When the PI0H bit is set to 1 by masking the PI0L bit and unmasking the PI0H bit with the GPIN_M register, the GPIN bit of the INT register is set to 1. As a result, an interrupt is reported. The PIN0L and PIN0H bits of the GPIN register are not latched. PRELIMINARY NEC confidential and Proprietary...

  • Page 147: Alarm Insertion / Detection Pins

    Signal Name Function Alarm signal output. RALMA 0-3 The errors to be indicated are selected by using the RALMR register. RALMB 0-3 RALMx 0 corresponds to PORT0, while RALMx 3 corresponds to RALMC 0-3 PORT3. PRELIMINARY NEC confidential and Proprietary...

  • Page 148: Management Interface

    Bit [15:0] Invalid Bit [15:0] Bit [31:16] Invalid Bit [31:16] Invalid (b) Big endian (MIFM=”1”) Address UWE_B Data AD [31:16] AD [15:0] Bit [31:16] Bit [15:0] Bit [31:16] Invalid Invalid Bit [15:0] Invalid Bit [15:0] PRELIMINARY NEC confidential and Proprietary...

  • Page 149: Access Timing

    µPD98413 negates RDY_B, and AD[31:0] go into a high-impedance state. At the next rising of MCLK, RDY_B goes in to a high-impedance state. When the µPD98413 negate RDY_B, the microprocessor can deassert CS_B. The microprocessor must deassert CS_B at least 1clock cycle. Figure 4-26. Read Access Timing PRELIMINARY NEC confidential and Proprietary...
  • Page 150 CHAPTER 4 INTERFACES MCLK( AD[31:0](I/O) Address Data Address CS_B( UWE_B( R/W_B( RDY_B( PRELIMINARY NEC confidential and Proprietary...

  • Page 151: Interrupt

    GEV, ICT and ICR registers and detailed cause register are set or reset depending on the detection status of an alarm or fault. In the default mode, all the causes are masked. PRELIMINARY NEC confidential and Proprietary...
  • Page 152 Table 4-7. Interrupt Port Register Register Outline • This register indicates the port of an interrupt occurrence. Interrupt register • If any of the bits of this register is set to 1, the interrupt signal (INT_B) is activated. (INT) PRELIMINARY NEC confidential and Proprietary...
  • Page 153 • This register indicates that general event has terminated. General event termination • When at least one bit in the TGE register is set to 1, the TGE bit in the GEV register is set. register (TGE) PRELIMINARY NEC confidential and Proprietary...
  • Page 154 Detection and termination of Path TIU Detection and termination of Path TIM Detection of the B3 error Detection of the B3 counter overflow Reception of Path REI Detection of the Path REI counter overflow Storing J1 message has been completed. PRELIMINARY NEC confidential and Proprietary...
  • Page 155 Detection of the transmit FIFO-RAM parity error. General event Detection and termination of the port detection. Detection and termination of the busy status due to port reset. General-purpose Change in the PIN0-PIN7 input level GPIN input pin level change PRELIMINARY NEC confidential and Proprietary...
  • Page 156 Table 4-11. Set and Reset Conditions of Detailed Cause Register and interrupt cause register Register Set Condition Reset Condition Event detection Cleared by CPU DSLER register DPPER register DAPER register DAPET register Event termination Cleared by CPU TSLER register TPPER register TAPER register PRELIMINARY NEC confidential and Proprietary...
  • Page 157 LOS bit of the SSLER register. Figure 4-28. Bit Operations of DSLER and TSLER Registers LOS Event DSLER [LOS Bit] TSLER [LOS Bit] SSLER [LOS Bit] Cleaed by CPU Interrupt Signal (INT_B) PRELIMINARY NEC confidential and Proprietary...
  • Page 158 PICR register, and masking of the PICR register masks asserting the interrupt signal active. By default, all the bits are set to 1, meaning that all the interrupt causes are masked. PRELIMINARY NEC confidential and Proprietary...

  • Page 159: Chapter 5 Registers

    In this document, the following two descriptions are also used to indicate the same overhead byte in the SDH/SONET frame. Description <1> 1st H1 2nd H1 3rd H1 47th H1 48th H1 1st H1 2nd H1 Description <2> H1#1 H1#2 H1#3 H1#47 H1#48 H1#1 H1#2 PRELIMINARY NEC confidential and Proprietary...

  • Page 160: Register Map

    J1PTN J1 trace message synchronous pattern 0D0A0000 0088 0488 0888 0C88 MDATMR Receive ATM mode 000000A8 008C 048C 088C 0C8C DCHP Drop cell header pattern 00000100 0090 0490 0890 0C90 MDPOSR Receive POS mode 00000000 PRELIMINARY NEC confidential and Proprietary...
  • Page 161 Transmit trace message command 00000000 011C 051C 091C 0D1C TMBR Receive trace message buffer 00000000 0120 0520 0920 0D20 TMDR Receive trace message buffer data 00000000 0124 0524 0924 0D24 CMTMR Receive trace message command 00000000 PRELIMINARY NEC confidential and Proprietary...
  • Page 162 Receive section and line layer event termination read clear 01D8 05D8 09D8 0DD8 TSLER_RCE Receive section and line layer event termination 00000FFF read clear enable 01DC 05DC 09DC 0DDC TSLER_M Receive section and line layer event termination 00000FFF mask PRELIMINARY NEC confidential and Proprietary...
  • Page 163 0294 TGE_RC General event termination read clear 00000000 0298 TGE_RCE General event termination read clear enable 00000FFF 029C TGE_M General event termination mask 00000FFF 02A0 General event status 00000FF0 02A4 IAADR Illegal access address 00000000 PRELIMINARY NEC confidential and Proprietary...
  • Page 164 0308 0708 0B08 0F08 FOPCR Receive FIFO overflow cell/packet counter load 00000000 030C 070C 0B0C 0F0C SPCR Receive short packet counter load 00000000 0310 0710 0B10 0F10 LPCR Receive long packet counter load 00000000 PRELIMINARY NEC confidential and Proprietary...
  • Page 165 Receive J1 drop 00000000 038C 078C 0B8C 0F8C Receive C2 drop 00000000 0390 0790 0B90 0F90 G1F2H4R Receive G1, F2 and H4 drop 00000000 0394 0794 0B94 0F94 Z345R Receive Z3, Z4 and Z5 drop 00000000 PRELIMINARY NEC confidential and Proprietary...

  • Page 166: Register Summary

    CHAPTER 5 REGISTERS 5.2 Register summary PRELIMINARY NEC confidential and Proprietary...
  • Page 167 CHAPTER 5 REGISTERS PRELIMINARY NEC confidential and Proprietary...
  • Page 168 CHAPTER 5 REGISTERS PRELIMINARY NEC confidential and Proprietary...

  • Page 169: Function Of Registers

    CHAPTER 5 REGISTERS 5.3 Function of Registers Device general mode register (MDDGEN) Common register The MDDGEN register sets the modes related to general operation of uPD98413. Register Address Access Default Name MDDGEN 0000H 00000080 H Reserved GPIOM[7:0] Reserved Reserved APIMM APIM MIFM...
  • Page 170 1: Enables the transmit function of the port2 of the PD98413. 0: Disable P2ET µ 1: Enables the transmit function of the port1 of the PD98413. 0: Disable P1ET µ 1: Enables the transmit function of the port0 of the PD98413. 0: Disable P0ET PRELIMINARY NEC confidential and Proprietary...
  • Page 171 Set to 0. µ 1: Executes software reset of the all functions of the PD98413. The uPD98413 is the reset condition while this bit is set to 1. Set 0 to this bit to return the normal operation. 0: Normal operation...
  • Page 172 1: Executes software reset of the transmit function of the port0 excepted TxPLL function. This function is the reset condition while this bit is set to 1. Set 0 to this bit to return the normal operation. 0: Normal operation PRELIMINARY NEC confidential and Proprietary...
  • Page 173 PD98413 is stored in the VER register. Register Address Access Default Name 000CH Reserved Reserved Field Function Default D31- Reserved D11-D8 Product version. D7-D4 Major version. D3-D0 Minor version. Note that contact NEC for the current version. PRELIMINARY NEC confidential and Proprietary...
  • Page 174 1: Outputs a high level from the PIO1 pin. 0: Outputs a low level from the pin. POUT0 1: Outputs a high level from the PIO0 pin. 0: Outputs a low level from the pin. PRELIMINARY NEC confidential and Proprietary...
  • Page 175 D8-D3 Reserved Set to 0. SLLPM Sets Line loopback mode of the SEDRDES block. Normal operation LPTM Sets the looptime mode using the receive clock for transmit. 1: Looptime 0: Normal Reserved Set to 0. PRELIMINARY NEC confidential and Proprietary...
  • Page 176 Controls the function of the Line DCC insert interface. 1: Enable 0: Disable SDCCE Controls the function of the Section DCC insert interface. 1: Enable 0: Disable Controls the function of the OH insert interface. 1: Enable 0: Disable PRELIMINARY NEC confidential and Proprietary...
  • Page 177 Controls the function of the Line DCC extract interface. 1: Enable 0: Disable SDCCE Controls the function of the Section DCC extract interface. 1: Enable 0: Disable Controls the function of the OH extract interface. 1: Enable 0: Disable PRELIMINARY NEC confidential and Proprietary...
  • Page 178 1: LOP event is indicated. 0: LOP event is not indicated. PSBF 1: PSBF event is indicated. 0: PSBF event is not indicated. LRDI 1: Line RDI event is indicated. 0: Line RDI event is not indicated. PRELIMINARY NEC confidential and Proprietary...
  • Page 179 0: Section TIM event is not indicated. 1: LOF event is indicated. 0: LOF event is not indicated. 1: OOF event is indicated. 0: OOF event is not indicated. 1: LOS event is indicated. 0: LOS event is not indicated. PRELIMINARY NEC confidential and Proprietary...
  • Page 180 1: Inserts FFH. 0: Inserts 00H. Reserved Set to 0. Selects a value to be inserted in the 4th Z0 to 11th Z0 bytes of the transmit overhead. 1: Inserts AAH. 0: Sequentially inserts 5 to 36. PRELIMINARY NEC confidential and Proprietary...
  • Page 181 Selects even or odd parity for BIP-96 (B2) parity operation of transmit line. 1: Odd parity 0: Even parity UUBM Selects a value to be inserted in the unused byte area of the transmit overhead. 1: Inserts FFH. 0: Inserts 00H. PRELIMINARY NEC confidential and Proprietary...
  • Page 182 Port0: Port1: Port2: Port3: MDPTRT 0048H 0448H 0848H 0C48H 00000000 H Reserved Reserved SS[1:0] Field Function Default D31-D2 Reserved Set to 0. D1-D0 SS[1:0] Sets the contents of the SS bits of the transmit pointer. PRELIMINARY NEC confidential and Proprietary...
  • Page 183 Selects even or odd parity for BIP-8 (B3) parity operation of transmit path. 1: Odd parity 0: Even parity FSBM Selects a value to be inserted in the Fixed Stuff byte area of the transmit frame. 1: Inserts 00H. 0: Inserts FFH. PRELIMINARY NEC confidential and Proprietary...
  • Page 184 Controls the HEC insertion to a transmit cell. 1: Disabled 0: Enabled CSCM Controls scramble of a cell. 1: Not scramble 0: Scramble IVCM Selects the format of an invalid cell to be transmitted. 1: Unassigned cell 0: Idle cell PRELIMINARY NEC confidential and Proprietary...
  • Page 185 0: Inserts FCS field. ADRM Controls the insertion of Address and Control fields in the transmit packet. 1: Disabled. Address and Control fields are not inserted in the transmit packet. 0: Inserts Address and Control fields. PRELIMINARY NEC confidential and Proprietary...
  • Page 186 000003FF H Reserved CTLIN[7:0] ADRIN[7:0] Field Function Default D31- Reserved Set to 0. Sets the Control value inserted into the transmit packet. D15-D8 CTLIN[7:0] Sets the Address value inserted into the transmit packet. D7-D0 ADRIN[7:0] PRELIMINARY NEC confidential and Proprietary...
  • Page 187 HPTNT 005CH 045CH 085CH 0C5CH 00000000 H Reserved Reserved SPTN[7:0] Field Function Default D31- Reserved Set to 0. Sets the suspended pattern during the packet transmission. D7-D0 SPTN[7:0] Set the value except “5D”, “5E”, “7D”. PRELIMINARY NEC confidential and Proprietary...
  • Page 188 Selects whether UDF is used in the format of the transmit cell to be transferred via the ATM interface. 1: Used 0: Not used PARM Selects even or odd parity for the parity operation of the transmit ATM/POS interface. 1: Even 0: Odd PRELIMINARY NEC confidential and Proprietary...
  • Page 189 (32-bit width) for the transmit FIFO space is lower than this field. POS mode: Sets the high threshold which the TPA signal is deasserted when the number of words (32-bit width) for the transmit FIFO space is lower than this field. PRELIMINARY NEC confidential and Proprietary...
  • Page 190 Set to 0. D8-D0 PINI[7:0] Sets the initial number of bytes when uPD98413 start to transmit the POS packet. 10 H The uPD98413 start to transmit the data when either the number of words (32-bit width) stored in the transmit FIFO exceeds this field or a complete packet is stored in the FIFO.
  • Page 191 Sets the transmit port address for UTOPIA. Port1: 1 POS-PHY mode: Port2: 2 Sets the polling address for POS-PHY. Port3: 3 IADR [7:0] Sets the transmit in-band port address. Port0: 0 Port1: 1 Port2: 2 Port3: 3 PRELIMINARY NEC confidential and Proprietary...
  • Page 192 Selects the size of the receive J0 section trace message. 1: 16 bytes 0: 64 bytes Selects even or odd parity for BIP-8 (B1) parity operation of receive section. 1: Odd parity 0: Even parity PRELIMINARY NEC confidential and Proprietary...
  • Page 193 Includes low level of the CD pin input in the LOS detection condition. 1: LOS status if the CD pin input goes low. 0: Not LOS status even if the CD pin input goes low. PRELIMINARY NEC confidential and Proprietary...
  • Page 194 Sets the synchronous pattern of J0 trace message. D31- J0PTN[15:0 0D0A H Sets the mask value of the synchronous pattern. D15-D0 J0M[15:0] 0000 H When the bits of this field is set to 1, the corresponding bits of synchronous pattern are masked PRELIMINARY NEC confidential and Proprietary...
  • Page 195 Selects even or odd parity for BIP-96 (B2) parity operation of receive line. 1: Odd parity 0: Even parity Controls if ignored of the bit1 in the received M1 bytes when detect the Line REI. 1: Ignored 0: Not ignored PRELIMINARY NEC confidential and Proprietary...
  • Page 196 H1#12 and H2#12 Concatenation Interpretation 1: Not include 0: include LOPT Selects the LOP termination condition whether include 3×conc_ind of all H1#2 and H2#2 to H1#12 and H2#12 Concatenation Interpretation. 1: Not include 0: Include PRELIMINARY NEC confidential and Proprietary...
  • Page 197 3 flames. 1: Not include NDF_enable, incr_ind and decr_ind is not receive at least 3 flames. 0: Include NDF_enable, incr_ind and decr_ind is not receive at least 3 flames. PRELIMINARY NEC confidential and Proprietary...
  • Page 198 Specifies whether the first pattern of a message or end pattern is selected as a synchronization pattern when the J1 path trace message is received. 1: Selects the first word of the message as a synchronization pattern. 0: Selects the last word of the message as a synchronization pattern. PRELIMINARY NEC confidential and Proprietary...
  • Page 199 Selects the size of the receive J1 path trace message. 1: 16 bytes 0: 64 bytes Selects even or odd parity for BIP-8 (B3) parity operation of receive line. 1: Odd parity 0: Even parity PRELIMINARY NEC confidential and Proprietary...
  • Page 200 Sets the synchronous pattern of J1 trace message. D31- J1PTN[15:0 0D0AH Sets the mask value of the synchronous pattern. D15-D0 J1M[15:0] 0000H When the bits of this field is set to 1, the corresponding bits of synchronous pattern are masked PRELIMINARY NEC confidential and Proprietary...
  • Page 201 0: Corrects bit error and passes cell. ε D1-D0 HECDC[1:0] Changes the number of recovery stages from "detection mode" to "correction mode" in HEC verification status transition. 11: Setting prohibited 10: 4 01: 2 00: 1 PRELIMINARY NEC confidential and Proprietary...
  • Page 202 This field masks the high-order eight bits. 0000 The bit of the cell header that is set to 1 in this area is not verified with the bit setting D3-D1 PTIM[2:0] of the high-order eight bits. CLPM PRELIMINARY NEC confidential and Proprietary...
  • Page 203 1: Disabled. Address and Control fields are not checked in the receive packet. 0: Checks Address and Control fields. If Address and Control errors occur, the packet is dropped and the error is indicated by interrupt. PRELIMINARY NEC confidential and Proprietary...
  • Page 204 Port3: HPTNR 0098 H 0498 H 0898 H 0C98 H 00000000 H Reserved Reserved SPTN[7:0] Field Function Default D31- Reserved Set to 0. Sets the expected value of the suspended pattern. D7-D0 SPTN[7:0] 00 H PRELIMINARY NEC confidential and Proprietary...
  • Page 205 D23-D0 LLEN[23:0] Sets the maximum packet length in byte units. Packets larger than this length are 05FCH indicated with long packet error. This length is defined as the number of payload bytes received POS packet. PRELIMINARY NEC confidential and Proprietary...
  • Page 206 Selects whether UDF is used in the format of the receive cell to be transferred via the ATM interface. 1: Used 0: Not used PARM Selects even or odd parity for the parity operation of the receive ATM/POS interface. 1: Even 0: Odd PRELIMINARY NEC confidential and Proprietary...
  • Page 207 Set to 0. PINI[7:0] Sets the initial number of words (32-bit width) when uPD98413 start to send the received POS packet to the POS device via receive POS interface. The uPD98413 start to send the data when either the number of words (32-bit width) stored in the receive FIFO exceeds this field or a complete packet is stored in the FIFO.
  • Page 208 Port3: 3 H IADR[7:0] UTOPIA mode: Port0: 00 H Sets the value of TAG field added to the receive cell. Port1: 01 H POS-PHY mode: Port2: 02 H Sets the receive in-band port address. Port3: 03 H PRELIMINARY NEC confidential and Proprietary...
  • Page 209 1: Transmission of Line RDI frame. Line RDI frames are successively transmitted while this bit is set to 1. 0: Normal operation LAIS 1: Transmission of Line AIS frame. Line AIS frames are successively transmitted while this bit is set to 1. 0: Normal operation PRELIMINARY NEC confidential and Proprietary...
  • Page 210 1: Transmits pseudo frame for OOF/LOF generation. Pseudo frames are successively transmitted while this bit is 1. 0: Normal operation PLOS 1: Transmits pseudo frame for LOS generation. Pseudo frames are successively transmitted while this bit is 1. 0: Normal operation PRELIMINARY NEC confidential and Proprietary...
  • Page 211 0: Normal operation PB2E 1: Transmits pseudo frame for B2 error generation. Pseudo frames are successively transmitted while this bit is 1. Pseudo error frames are set in the B2 field. 0: Normal operation PRELIMINARY NEC confidential and Proprietary...
  • Page 212 0CCC H 00000000 H Reserved Reserved PLOP Field Function Default D31-D1 Reserved Set to 0. PLOP 1: Transmits pseudo frame for LOP generation. Pseudo frames are successively transmitted while this bit is 1. 0: Normal operation PRELIMINARY NEC confidential and Proprietary...
  • Page 213 0: Normal operation PB3E 1: Transmits pseudo frame for B3 error generation. Pseudo frames are successively transmitted while this bit is 1. Pseudo error frames are set in the B3 field. 0: Normal operation PRELIMINARY NEC confidential and Proprietary...
  • Page 214 0CD4 H 00000000 H Reserved Reserved POCD Field Function Default D31-D1 Reserved Set to 0. POCD 1: Transmits pseudo frame for OCD/LCD generation. Pseudo frames are successively transmitted while this bit is 1. 0: Normal operation PRELIMINARY NEC confidential and Proprietary...
  • Page 215 00: Disable D7-D2 Reserved Set to 0. D1-D0 SFM[1:0] Selects the source and enable which SF condition of the bit error rate monitoring is detected. 11: B3 errors 10: B2 errors 01: B1 errors 00: Disable PRELIMINARY NEC confidential and Proprietary...
  • Page 216 Sets parameter "MD" for SF detection. MD defines the number of consecutive events as SF detection condition, in each of which LD or more errors are detected in one frame to be monitored (successive ND frames). PRELIMINARY NEC confidential and Proprietary...
  • Page 217 Sets parameter "MT" for SF termination. MT defines the number of consecutive events as SF termination condition, in each of which less than LT errors are detected in one frame to be monitored (successive NT frames). PRELIMINARY NEC confidential and Proprietary...
  • Page 218 Sets parameter "MD" for SD detection. MD defines the number of consecutive events as SD detection condition, in each of which LD or more errors are detected in one frame to be monitored (successive ND frames). PRELIMINARY NEC confidential and Proprietary...
  • Page 219 Sets parameter "MT" for SD termination. MT defines the number of consecutive events as SD termination condition, in each of which less than LT errors are detected in one frame to be monitored (successive NT frames). PRELIMINARY NEC confidential and Proprietary...
  • Page 220 Reserved Set to 0. BSEL Selects the section or path trace message buffer. 1: J1 buffer 0: J0 buffer D7-D6 Reserved Set to 0. BADR[5:0] Sets the offset address of the trace message buffer. D5-D0 PRELIMINARY NEC confidential and Proprietary...
  • Page 221 D31-D0 When read access, the data will be read from the trace message buffer set by TMBT register. When write access, the data will be written into the trace message buffer set by TMBT register. PRELIMINARY NEC confidential and Proprietary...
  • Page 222 0: Disable J1STAT Starts to transmit new path trace message. 1: Transmits new message 0: Does not change message J0STAT Starts to transmit new section trace message. 1: Transmits new message 0: Does not change message PRELIMINARY NEC confidential and Proprietary...
  • Page 223 Selects the section or path trace message buffer. 1: J1 buffer 0: J0 buffer Reserved Set to 0. BTYP Selects the message buffer. 1: Accepted buffer 0: Expected buffer BADR[5:0] Sets the offset address of the trace message buffer. 00 H D5-D0 PRELIMINARY NEC confidential and Proprietary...
  • Page 224 Indicated and sets to lock the accepted buffer of the path trace message. 1: Lock 0: Unlock J0LOCK Indicated and sets to lock the accepted buffer of the section trace message. 1: Lock 0: Unlock PRELIMINARY NEC confidential and Proprietary...
  • Page 225 1: Indicates that the transmit interrupt occurs in Port1. 0: Corresponding ICT register is all 0. P0ICT 1: Indicates that the transmit interrupt occurs in Port0. 0: Corresponding ICT register is all 0. Note : Depends on the corresponding register status. PRELIMINARY NEC confidential and Proprietary...
  • Page 226 P1ICR 1: Mask 0: Unmask P0ICR 1: Mask 0: Unmask APIET 1: Mask 0: Unmask P3ICT 1: Mask 0: Unmask P2ICT 1: Mask 0: Unmask P1ICT 1: Mask 0: Unmask P0ICT 1: Mask 0: Unmask PRELIMINARY NEC confidential and Proprietary...
  • Page 227 Port0: Port1: Port2: Port3: ICT_M 0154 H 0554 H 0954 H 0D54 H 00000001 H Mask register Reserved Reserved DAPET Field Function Default Reserved All 0 D31-D1 Set to 0 DAPET 1: Mask 0: Unmask PRELIMINARY NEC confidential and Proprietary...
  • Page 228 1: Detects the wrong order for SOP and EOP of port 3. 0: Does not detect. UTOPIA mode (APIM=1 in MDDGEN): This field is no function and always 0. uPD98413 does not indicate this error. P2SEPE POS-PHY mode (APIM=0 in MDDGEN): 1: Detects the wrong order for SOP and EOP of port 2.
  • Page 229 1: Detects the wrong order for SOP and EOP of port 1. 0: Does not detect. UTOPIA mode (APIM=1 in MDDGEN): This field is no function and always 0. uPD98413 does not indicate this error. P0SEPE POS-PHY mode (APIM=0 in MDDGEN): 1: Detects the wrong order for SOP and EOP of port 0.
  • Page 230 0: Does not detect. Packet on POS-PHY mode (APIM=0 in MDDGEN and APM=0 in MDPGEN): This field is no function and always 0. uPD98413 does not indicate this error. P3PEB 1: Detects a parity error in the transmit FIFO RAM-B of port 3.
  • Page 231 P3PEA 1: Enable 0: Disable P2PEB 1: Enable 0: Disable P2PEA 1: Enable 0: Disable P1PEB 1: Enable 0: Disable P1PEA 1: Enable 0: Disable P0PEB 1: Enable 0: Disable P0PEA 1: Enable 0: Disable PRELIMINARY NEC confidential and Proprietary...
  • Page 232 P3PEA 1: Mask 0: Unmask P2PEB 1: Mask 0: Unmask P2PEA 1: Mask 0: Unmask P1PEB 1: Mask 0: Unmask P1PEA 1: Mask 0: Unmask P0PEB 1: Mask 0: Unmask P0PEA 1: Mask 0: Unmask PRELIMINARY NEC confidential and Proprietary...
  • Page 233 0: TSLER register is all 0. DSLER 1: Indicates that the bits of the DSLER register are set. 0: DSLER register is all 0. Note : Default value of this register is depends on status of corresponding register. PRELIMINARY NEC confidential and Proprietary...
  • Page 234 0: Unmask DAPER 1: Mask 0: Unmask Reserved Set to 1 TPPER 1: Mask 0: Unmask DPPER 1: Mask 0: Unmask Reserved Set to 1 TSLER 1: Mask 0: Unmask DSLER 1: Mask 0: Unmask PRELIMINARY NEC confidential and Proprietary...
  • Page 235 0: Does not detect. POS-PHY mode (APIM=0 in MDDGEN): This field is no function and always 0. uPD98413 does not indicate this error. P2PSE UTOPIA mode (APIM=1 in MDDGEN): 1: Detects that port2 is selected although the corresponding RXCLAV is low (not active).
  • Page 236 1: Detects that RXENB_B is deasserted while a cell transfer of port 3. 0: Does not detect. POS-PHY mode (APIM=0 in MDDGEN): This field is no function and always 0. uPD98413 does not indicate this error. P2CE UTOPIA mode (APIM=1 in MDDGEN): 1: Detects that RXENB_B is deasserted while a cell transfer of port 2.
  • Page 237 1: Enable 0:disable P3PEB 1: Enable 0:disable P3PEA 1: Enable 0:disable P2PEB 1: Enable 0:disable P2PEA 1: Enable 0:disable P1PEB 1: Enable 0:disable P1PEA 1: Enable 0:disable P0PEB 1: Enable 0:disable P0PEA 1: Enable 0:disable PRELIMINARY NEC confidential and Proprietary...
  • Page 238 P3PEA 1: mask 0: unmask P2PEB 1: mask 0: unmask P2PEA 1: mask 0: unmask P1PEB 1: mask 0: unmask P1PEA 1: mask 0: unmask P0PEB 1: mask 0: unmask P0PEA 1: mask 0: unmask PRELIMINARY NEC confidential and Proprietary...
  • Page 239 Indicates the input level of the PIO1 pin. 1: High 0: Low PIN0H Indicates the input level of the PIO0 pin. 1: High 0: Low Note: the default value of this register is depends on input level of corresponding PIO pins PRELIMINARY NEC confidential and Proprietary...
  • Page 240 PIN6H 1: mask 0: unmask PIN5H 1: mask 0: unmask PIN4H 1: mask 0: unmask PIN3H 1: mask 0: unmask PIN2H 1: mask 0: unmask PIN1H 1: mask 0: unmask PIN0H 1: mask 0: unmask PRELIMINARY NEC confidential and Proprietary...
  • Page 241 The GEV_M register is mask register of GEV register. Register Address Access Default Function Name GEV_M 01A4 H 00000003 H Mask register Reserved Reserved Field Function Default Reserved Reserved D31-D2 1: mask 0: unmask 1: mask 0: unmask PRELIMINARY NEC confidential and Proprietary...
  • Page 242 0: Does not detect. VPCT 1: Detects occurrence of an overflow in transmit valid cell/packet counter. 0: Does not detect. ABOE 1: Detects occurrence of transmit abort packet due to a transmit FIFO underflow. 0: Does not detect. PRELIMINARY NEC confidential and Proprietary...
  • Page 243 Reserved FUPCT APCT VPCT ABOE Field Function Default Reserved All 0 D31-D4 Set to 0. FUPCT 1: enable 0: disable APCT 1: enable 0: disable VPCT 1: enable 0: disable ABOE 1: enable 0: disable PRELIMINARY NEC confidential and Proprietary...
  • Page 244 Reserved FUPCT APCT VPCT ABOE Field Function Default Reserved All 0 D31-D7 Set to 0. FUPCT 1: mask 0: unmask APCT 1: mask 0: unmask VPCT 1: mask 0: unmask ABOE 1: mask 0: unmask PRELIMINARY NEC confidential and Proprietary...
  • Page 245 1: Detects occurrence of OOF event. 0: Does not detect. 1: Detects occurrence of LOS event. 0: Does not detect. Note: the default value of this register is depends on input level of the CD pin. PRELIMINARY NEC confidential and Proprietary...
  • Page 246 1: Enable 0: Disable LRDI 1: Enable 0: Disable LAIS 1: Enable 0: Disable STIU 1: Enable 0: Disable STIM 1: Enable 0: Disable 1: Enable 0: Disable 1: Enable 0: Disable 1: Enable 0: Disable PRELIMINARY NEC confidential and Proprietary...
  • Page 247 1: Mask 0: Unmask LRDI 1: Mask 0: Unmask LAIS 1: Mask 0: Unmask STIU 1: Mask 0: Unmask STIM 1: Mask 0: Unmask 1: Mask 0: Unmask 1: Mask 0: Unmask 1: Mask 0: Unmask PRELIMINARY NEC confidential and Proprietary...
  • Page 248 1: Detects termination of OOF event. 0: Does not detect. 1: Detects termination of LOS event. 0: Does not detect. Note: the default value of this register is depends on the input level of the CD pin. PRELIMINARY NEC confidential and Proprietary...
  • Page 249 1: enable 0: disable LRDI 1: enable 0: disable LAIS 1: enable 0: disable STIU 1: enable 0: disable STIM 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable PRELIMINARY NEC confidential and Proprietary...
  • Page 250 1: mask 0: unmask LRDI 1: mask 0: unmask LAIS 1: mask 0: unmask STIU 1: mask 0: unmask STIM 1: mask 0: unmask 1: mask 0: unmask 1: mask 0: unmask 1: mask 0: unmask PRELIMINARY NEC confidential and Proprietary...
  • Page 251 1: OOF event in progress 0: OOF event is not detected. 1: LOS event in progress 0: LOS event is not detected. Note: the default value of this register is depends on input level of the CD pin. PRELIMINARY NEC confidential and Proprietary...
  • Page 252 OPRDI 1: Detects occurrence of One-bit Path RDI event. 0: Does not detect. PAIS 1: Detects occurrence of Path AIS event. 0: Does not detect. 1: Detects occurrence of LOP event. 0: Does not detect. PRELIMINARY NEC confidential and Proprietary...
  • Page 253 0: Disable PPLM 1: Enable 0: Disable ERDIP 1: Enable 0: Disable ERDIC 1: Enable 0: Disable ERDIS 1: Enable 0: Disable OPRDI 1: Enable 0: Disable PAIS 1: Enable 0: Disable 1: Enable 0: Disable PRELIMINARY NEC confidential and Proprietary...
  • Page 254 0: unmask PPLM 1: mask 0: unmask ERDIP 1: mask 0: unmask ERDIC 1: mask 0: unmask ERDIS 1: mask 0: unmask OPRDI 1: mask 0: unmask PAIS 1: mask 0: unmask 1: mask 0: unmask PRELIMINARY NEC confidential and Proprietary...
  • Page 255 OPRDI 1: Detects termination of One-bit Path RDI event. 0: Does not detect. PAIS 1: Detects termination of Path AIS event. 0: Does not detect. 1: Detects termination of LOP event. 0: Does not detect. PRELIMINARY NEC confidential and Proprietary...
  • Page 256 0: Disable PPLM 1: Enable 0: Disable ERDIP 1: Enable 0: Disable ERDIC 1: Enable 0: Disable ERDIS 1: Enable 0: Disable OPRDI 1: Enable 0: Disable PAIS 1: Enable 0: Disable 1: Enable 0: Disable PRELIMINARY NEC confidential and Proprietary...
  • Page 257 0: Unmask PPLM 1: Mask 0: Unmask ERDIP 1: Mask 0: Unmask ERDIC 1: Mask 0: Unmask ERDIS 1: Mask 0: Unmask OPRDI 1: Mask 0: Unmask PAIS 1: Mask 0: Unmask 1: Mask 0: Unmask PRELIMINARY NEC confidential and Proprietary...
  • Page 258 1: One-bit Path RDI event in progress 0: One-bit Path RDI event is not detected. PAIS 1: Path AIS event in progress 0: Path AIS event is not detected. 1: LOP event in progress 0: LOP event is not detected. PRELIMINARY NEC confidential and Proprietary...
  • Page 259 ABOE 1: Detects occurrence of receive abort packet. 0: Does not detect. Reserved D15-D2 Reserved. 1: Detects occurrence of LCD event. 0: Does not detect. 1: Detects occurrence of OCD event. 0: Does not detect. PRELIMINARY NEC confidential and Proprietary...
  • Page 260 1: Enable 0: Disable 1: Enable 0: Disable FCSE 1: Enable 0: Disable ADRE 1: Enable 0: Disable ABOE 1: Enable 0: Disable D15-D2 Reserved Reserved. All 0 1: Enable 0: Disable 1: Enable 0: Disable PRELIMINARY NEC confidential and Proprietary...
  • Page 261 0: Unmask 1: Mask 0: Unmask FCSE 1: Mask 0: Unmask ADRE 1: Mask 0: Unmask ABOE 1: Mask 0: Unmask D15-D2 Reserved Set to 0. All 0 1: Mask 0: Unmask 1: Mask 0: Unmask PRELIMINARY NEC confidential and Proprietary...
  • Page 262 Port1: Port2: Port3: TAPER_RCE 0258 H 0658 H 0A58 H 0E58 H 00000003 H Read clear enable Reserved Reserved Field Function Default Reserved Set to 0. All 0 D31-D2 1: Enable 0:Disable 1: Enable 0:Disable PRELIMINARY NEC confidential and Proprietary...
  • Page 263 Port0: Port1: Port2: Port3: TAPER_M 025C H 065C H 0A5C H 0E5C H 00000003 H Mask register Reserved Reserved Field Function Default Reserved All 0 D31-D2 Set to 0. 1: Mask 0:Unmask 1: Mask 0:Unmask PRELIMINARY NEC confidential and Proprietary...
  • Page 264 0E70 H Read-only Reserved Reserved Field Function Default Reserved Reserved All 0 D31-D2 1: LCD event in progress 0: LCD event is not detected. 1: OCD event in progress 0: OCD event is not detected. PRELIMINARY NEC confidential and Proprietary...
  • Page 265 0: Does not detect. P0BSY 1: Detects that the receive function of port0 is busy due to port enable. 0: Does not detect. Note: the default value of this register is depends on General event. PRELIMINARY NEC confidential and Proprietary...
  • Page 266 1: Enable 0:Disable P3INIT 1: Enable 0:Disable P2INIT 1: Enable 0:Disable P1INIT 1: Enable 0:Disable P0INIT 1: Enable 0:Disable P3BSY 1: Enable 0:Disable P2BSY 1: Enable 0:Disable P1BSY 1: Enable 0:Disable P0BSY 1: Enable 0:Disable PRELIMINARY NEC confidential and Proprietary...
  • Page 267 P2INIT 1: Mask 0: Unmask P1INIT 1: Mask 0: Unmask P0INIT 1: Mask 0: Unmask P3BSY 1: Mask 0: Unmask P2BSY 1: Mask 0: Unmask P1BSY 1: Mask 0: Unmask P0BSY 1: Mask 0: Unmask PRELIMINARY NEC confidential and Proprietary...
  • Page 268 1: Detects that the receive function of port1 is not busy due to port disable. 0: Does not detect. P0BSY 1: Detects that the receive function of port0 is not busy due to port disable. 0: Does not detect. PRELIMINARY NEC confidential and Proprietary...
  • Page 269 1: Enable 0:Disable P3INIT 1: Enable 0:Disable P2INIT 1: Enable 0:Disable P1INIT 1: Enable 0:Disable P0INIT 1: Enable 0:Disable P3BSY 1: Enable 0:Disable P2BSY 1: Enable 0:Disable P1BSY 1: Enable 0:Disable P0BSY 1: Enable 0:Disable PRELIMINARY NEC confidential and Proprietary...
  • Page 270 P2INIT 1: Mask 0: Unmask P1INIT 1: Mask 0: Unmask P0INIT 1: Mask 0: Unmask P3BSY 1: Mask 0: Unmask P2BSY 1: Mask 0: Unmask P1BSY 1: Mask 0: Unmask P0BSY 1: Mask 0: Unmask PRELIMINARY NEC confidential and Proprietary...
  • Page 271 1: The receive function of port1 is busy. 0: The receive function of port1 is not busy. P0BSY 1: The receive function of port0 is busy. 0: The receive function of port0 is not busy. PRELIMINARY NEC confidential and Proprietary...
  • Page 272 The IAADR register indicates the address of the illegal access. Register Address Access Default Name IAADR 02A4 H 00000000 H Reserved Reserved IAADR Field Function Default D31- Reserved Reserved All 0 D12-D0 IAADR Indicates the address of the illegal access. 0000 H PRELIMINARY NEC confidential and Proprietary...
  • Page 273 1: Loads the transmit abort packet counter. 0: Indicates completion of loading. VPCT ATM mode: 1: Loads the valid transmit cell counter. 0: Indicates completion of loading. POS mode: 1: Loads the valid transmit packet counter. 0: Indicates completion of loading. PRELIMINARY NEC confidential and Proprietary...
  • Page 274 This register reads the transmit abort packet counter value. Register Address Access Default Name Port0: Port1: Port2: Port3: APCT 02CC H 06CC H 0ACC H 0ECC H 00000000 H APCT [31:16] APCT [15:0] Field Function Default D31-D0 APCT Transmit abort packet counter. PRELIMINARY NEC confidential and Proprietary...
  • Page 275 This register reads the transmit FIFO underflow packet counter value. Register Address Access Default Name Port0: Port1: Port2: Port3: FUPCT 02D0 H 06D0 H 0AD0 H 0ED0 H 00000000 H FUPCT [31:16] FUPCT [15:0] Field Function Default D31-D0 FUPCT Transmit FIFO underflow packet counter. PRELIMINARY NEC confidential and Proprietary...
  • Page 276 1: Number of error frames 0: Number of error bits B1ECRM Selects the number of the error bits or frames counted by B1 error counter. 1: Number of error frames 0: Number of error bits PRELIMINARY NEC confidential and Proprietary...
  • Page 277 1: Loads the valid receive packet counter. 0: Indicates completion of loading. NFJCR 1: Loads the Negative Frequency Justification counter 0: Indicates completion of loading. PFJCR 1: Loads the Positive Frequency Justification counter 0: Indicates completion of loading. PRELIMINARY NEC confidential and Proprietary...
  • Page 278 1: Loads the B3 error counter. 0: Indicates completion of loading. B2ECR 1: Loads the B2 error counter. 0: Indicates completion of loading. B1ECR 1: Loads the B1 error counter. 0: Indicates completion of loading. PRELIMINARY NEC confidential and Proprietary...
  • Page 279 This register reads the B2 error counter value. B2 error count is selected from the number of error bits or frames. Register Address Access Default Name Port0: Port1: Port2: Port3: B2ECR 02E0 H 06E0 H 0AE0 H 0EE0 H 00000000H B2ECR [31:16] B2ECR [15:0] Field Function Default D31-D0 B2ECR B2 error counter. PRELIMINARY NEC confidential and Proprietary...
  • Page 280 This register reads the Line REI counter value. Line REI count is selected from the number of error bits or frames. Register Address Access Default Name Port0: Port1: Port2: Port3: LREICR 02E8 H 06E8 H 0AE8 H 0EE8 H 00000000 H LREICR [31:16] LREICR [15:0] Field Function Default D31-D0 LREICR Line REI counter. PRELIMINARY NEC confidential and Proprietary...
  • Page 281 This register reads the Positive Frequency Justification counter value. Register Address Access Default Name Port0: Port1: Port2: Port3: PFJCR 02F0 H 06F0 H 0AF0 H 0EF0 H 00000000H Reserved PFJCR [15:0] Field Function Default D31- Reserved D15-D0 PFJCR Positive Frequency Justification counter. PRELIMINARY NEC confidential and Proprietary...
  • Page 282 POS mode. Register Address Access Default Name Port0: Port1: Port2: Port3: VPCR 02F8 H 06F8 H 0AF8 H 0EF8 H 00000000 H VPCR [31:16] VPCR [15:0] Field Function Default D31-D0 VPCR Receive valid cell/packet counter. PRELIMINARY NEC confidential and Proprietary...
  • Page 283 Name Port0: Port1: Port2: Port3: AEPCR 0300 H 0700 H 0B00 H 0F00 H 00000000 H AEPCR [31:16] AEPCR [15:0] Field Function Default D31-D0 AEPCR Receive HEC error correct cell and address error packet counter. PRELIMINARY NEC confidential and Proprietary...
  • Page 284 This register reads the receive FCS error packet counter value. Register Address Access Default Name Port0: Port1: Port2: Port3: FEPCR 0304 0704 0B04 0F04 00000000H FEPCR [31:16] FEPCR [15:0] Field Function Default D31-D0 FEPCR Receive HEC error drop cell and FCS error packet counter. PRELIMINARY NEC confidential and Proprietary...
  • Page 285 This register reads the receive short packet counter value. Register Address Access Default Name Port0: Port1: Port2: Port3: SPCR 030C H 070C H 0B0C H 0F0C H 00000000 H SPCR [31:16] SPCR [15:0] Field Function Default D31-D0 SPCR Receive short packet counter. PRELIMINARY NEC confidential and Proprietary...
  • Page 286 This register reads the receive long packet counter value. Register Address Access Default Name Port0: Port1: Port2: Port3: LPCR 0310 H 0710 H 0B10 H 0F10 H 00000000 H LPCR [31:16] LPCR [15:0] Field Function Default D31-D0 LPCR Receive long packet counter. PRELIMINARY NEC confidential and Proprietary...
  • Page 287 Sets the data to be inserted at the position of the F1 byte of a transmit frame. D7-D0 E1[7:0] Sets the data to be inserted at the position of the E1 byte of a transmit frame. PRELIMINARY NEC confidential and Proprietary...
  • Page 288 Sets the data to be inserted at the position of the D2 byte of a transmit frame. D7-D0 D1[7:0] Sets the data to be inserted at the position of the D1 byte of a transmit frame. PRELIMINARY NEC confidential and Proprietary...
  • Page 289 PD98413 does not transmit alarm Line AIS or Line RDI, the values of K2[7:0] of this register are transmitted. D7-D0 K1[7:0] Sets the data to be inserted at the position of the K1 byte of a transmit frame. PRELIMINARY NEC confidential and Proprietary...
  • Page 290 Sets the data to be inserted at the position of the D8 byte of a transmit frame. D7-D0 D7[7:0] Sets the data to be inserted at the position of the D7 byte of a transmit frame. PRELIMINARY NEC confidential and Proprietary...
  • Page 291 Sets the data to be inserted at the position of the 1st Z2 byte of a transmit frame. D7-D0 S1[7:0] Sets the data to be inserted at the position of the S1 byte of a transmit frame. PRELIMINARY NEC confidential and Proprietary...
  • Page 292 Set the data to be inserted at the position of the G1 byte (bits 5 to 8) of a transmit µ frame. The PD98413 overwrites bits 5 to 7 when it transmits Path RDI because of command execution or automatic loopback. PRELIMINARY NEC confidential and Proprietary...
  • Page 293 Sets the data to be inserted at the position of the Z4 byte of a transmit frame. D7-D0 Z3[7:0] Sets the data to be inserted at the position of the Z3 byte of a transmit frame. PRELIMINARY NEC confidential and Proprietary...
  • Page 294 Reserved D15-D8 F1[7:0] Stores the receive F1 byte. This field is updated each time a frame is received. D7-D0 E1[7:0] Stores the receive E1 byte. This field is updated each time a frame is received. PRELIMINARY NEC confidential and Proprietary...
  • Page 295 The receive K2 byte is stored. D7-D0 K1[7:0] The receive K1 byte is stored. This register is updated when three contiguous frames containing the same K1 and K2 bytes are received after the contents of the register are changed. PRELIMINARY NEC confidential and Proprietary...
  • Page 296 Stores the receive D6 byte. This field is updated each time a frame is received. D15-D8 D5[7:0] Stores the receive D5 byte. This field is updated each time a frame is received. D7-D0 D4[7:0] Stores the receive D4 byte. This field is updated each time a frame is received. PRELIMINARY NEC confidential and Proprietary...
  • Page 297 Stores the receive D9 byte. This field is updated each time a frame is received. D15-D8 D8[7:0] Stores the receive D8 byte. This field is updated each time a frame is received. D7-D0 D7[7:0] Stores the receive D7 byte. This field is updated each time a frame is received. PRELIMINARY NEC confidential and Proprietary...
  • Page 298 Stores the receive D12 byte. This field is updated each time a frame is received. D15-D8 D11[7:0] Stores the receive D11 byte. This field is updated each time a frame is received. D7-D0 D10[7:0] Stores the receive D10 byte. This field is updated each time a frame is received. PRELIMINARY NEC confidential and Proprietary...
  • Page 299 D7-D0 Z2FD[7:0] Stores the receive 1st Z2 byte. This field is updated when six contiguous frames containing the same bit 6-7 of 1st Z2 byte are received after the contents of the register are changed. PRELIMINARY NEC confidential and Proprietary...
  • Page 300 0388 H 0788 H 0B88 H 0F88 H 00000000 H Reserved Reserved J1[7:0] Field Function Default D31-D8 Reserved D7-D0 J1[7:0] Stores the receive J1 byte. This field is updated each time a frame is received. PRELIMINARY NEC confidential and Proprietary...
  • Page 301 Stores the receive H4 byte. This field is updated each time a frame is received. D15-D8 F2[7:0] Stores the receive F2 byte. This field is updated each time a frame is received. D7-D0 G1[7:0] Stores the receive G1 byte. This field is updated each time a frame is received. PRELIMINARY NEC confidential and Proprietary...
  • Page 302 Stores the receive Z5 byte. This field is updated each time a frame is received. D15-D8 Z4[7:0] Stores the receive Z4 byte. This field is updated each time a frame is received. D7-D0 Z3[7:0] Stores the receive Z3 byte. This field is updated each time a frame is received. PRELIMINARY NEC confidential and Proprietary...
  • Page 303 CHAPTER 5 REGISTERS [MEMO] PRELIMINARY NEC confidential and Proprietary...

  • Page 304: Chapter 6 Jtag Boundary Scan

    • SAMPLE/PRELOAD instruction • Five pins dedicated to boundary scan • JCK (JTAG Clock) • JMS (JTAG Mode Select) • JDI (JTAG Data Input) • JDO (JTAG Data Output) • JRST_B (JTAG Reset)     PRELIMINARY NEC confidential and Proprietary...

  • Page 305: Internal Configuration Of Boundary Scan Circuit

    If this register is selected while the TAP controller is in Shift-DR state, data is output to the JDO pin starting from the LSB at the falling edge of the clock input to the JCK pin. PRELIMINARY NEC confidential and Proprietary...
  • Page 306 JCK pin. This pin is a tristate output pin and is controlled by the TAP controller. 6.3.5 JRST_B (JTAG Reset) Pin This pin asynchronously initializes the TAP controller. This reset signal sets the µPD98413 in the normal operation mode and the boundary register in non-operation state. PRELIMINARY NEC confidential and Proprietary...
  • Page 307 Remarks 1. "H" and "L" of the arrows indicating state transition in the above figure indicate the state of the JMS pin at the rising edge of the clock input to the JCK pin. 2. Numbers in ( ) in the above figure correspond to the explanation below. PRELIMINARY NEC confidential and Proprietary...
  • Page 308 If the JMS signal is held high at the rising edge of the JCK pin signal, the TAP controller enters the Select-IR-Scan state. While the controller is in this state, the instruction does not change. PRELIMINARY NEC confidential and Proprietary...
  • Page 309 The TAP controller remains in this state while the JMS pin signal is low. If the JMS pin signal is held high at the rising edge of the JCK pin signal, the TAP controller enters the Exit2-DR state. While the TAP controller is in this state, the instruction does not change. PRELIMINARY NEC confidential and Proprietary...
  • Page 310 If the JMS pin signal is held high at the rising edge of the JCK pin signal with the TAP controller in this state, the controller enters the Exit1-IR state. If the JMS pin signal is held low, the controller remains the Shift-IR state. PRELIMINARY NEC confidential and Proprietary...
  • Page 311 If the JMS pin signal is held low at the rising edge of the JCK pin signal, the TAP controller enters the Run-Test/Idle state. The Pause-DR controller state in (8) and Pause-IR controller state in (14) temporarily stop shifting of data in the bypass register, boundary scan register, or instruction register. PRELIMINARY NEC confidential and Proprietary...
  • Page 312 High impedance Run-Test/Idle Select-DR-Scan Select-IR-Scan Capture-IR Shift-IR Instruction register Active Exit1-IR Undefined High impedance Pause-IR Exit2-IR Update-IR Capture-DR Shift-DR Data register (boundary scan register, bypass register) Active Exit1-DR Undefined High impedance Pause-DR Exit2-DR Update-DR     PRELIMINARY NEC confidential and Proprietary...
  • Page 313 I n a c t i v e JDO enable signal JDO pin signal     Note TDR (Test Data Register): Boundary scan register and bypass register Remark : Don't care or undefined     PRELIMINARY NEC confidential and Proprietary...
  • Page 314 I n a c t i v e JDO enable signal JDO pin signal     Note TDR (Test Data Register): Boundary scan register and bypass register Remark : Don't care or undefined     PRELIMINARY NEC confidential and Proprietary...

  • Page 315: Instruction Register

    The JTAG boundary scan circuit of the mPD98414 can support only the following three instructions depending on the data set to the instruction register. • BYPASS instruction • EXTEST instruction • SAMPLE/PRELOAD instruction   Instruction Register Supported Instruction EXTEST instruction SAMPLE/PRELOAD instruction Unused (BYPASS instruction) BYPASS instruction PRELIMINARY NEC confidential and Proprietary...
  • Page 316 This instruction is specified by instruction data "01". This instruction can execute two functions, SAMPLE and PRELOAD, with a single instruction. 6.7.4 Boundary Scan Data Bit Definition NEC can supply the BSDL (Boundary Scan Description Language) file for the mPD98414 upon request. PRELIMINARY NEC confidential and Proprietary...
  • Page 317 CHAPTER 6 JTAG BOUNDARY SCAN [MEMO] PRELIMINARY NEC confidential and Proprietary...

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