Summary of Contents for NEC mPD4992
- Page 1 User’s Manual µ PD4992 8-bit Parallel I/O Calendar Clock Document No. S11812EJ4V0UM00 (4th edition) Date Published May 1998 N CP(K) © 1998 Printed in Japan...
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- Page 3 The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
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Page 5: Table Of Contents
CONTENTS CHAPTER 1 OUTLINE OF µ PD4992 ....................1.1 Features ..........................1.2 Pin Connections ........................ 1.3 Pin Functions ........................1.4 Block Diagram ........................1.5 Oscillation Stage and 15-Stage Binary Divider ............1.6 Register Configuration ..................... 1.7 Notes on Use ........................CHAPTER 2 OPERATIONS ....................... - Page 6 CHAPTER 4 ELECTRICAL SPECIFICATIONS AND INTERFACE ..........4.1 Crystal Oscillation Circuit ....................4.2 Oscillation Characteristics and Accuracy ..............4.2.1 Dependency on load capacitance ..................4.2.2 Dependency on temperature ....................4.3 Adjusting Oscillation Frequency ..................4.4 Backup Circuit ........................4.5 Power-Fail Circuit ......................
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Page 7: Chapter 1 Outline Of Μ Pd4992
CHAPTER 1 OUTLINE OF µ PD4992 The µ PD4992 is a CMOS IC that inputs or outputs 8-bit parallel real-time clock or calendar data from or to a microprocessor based system. This IC has seven types of internal counters: year, month, day, date, hour, minute, and second. The hour counter can operate in 12-hour or 24-hour mode. -
Page 8: Pin Connections
CHAPTER 1 OUTLINE OF µ PD4992 1.2 Pin Connections µ PD4992CX/ µ PD4992GS... -
Page 9: Pin Functions
CHAPTER 1 OUTLINE OF µ PD4992 1.3 Pin Functions Pin Symbol Pin Name Pin No. Function Chip select input Access to the internal registers is enabled when CS = L, = H. Chip select input Write signal input The contents of the data bus are written to the register selected by inputting an address at the rising edge of this signal. -
Page 10: Block Diagram
CHAPTER 1 OUTLINE OF µ PD4992 1.4 Block Diagram 15-Stage Binary Divider Time Counter Clock Stop TP Generator Data Bus Mode Register Controller Control Register Address Bus Address Controller Decoder... -
Page 11: Oscillation Stage And 15-Stage Binary Divider
CHAPTER 1 OUTLINE OF µ PD4992 1.5 Oscillation Stage and 15-Stage Binary Divider A reference frequency of 32.768 kHz is obtained by using a 32.768-kHz crystal resonator and a crystal oscillation circuit that uses a CMOS inverter. This reference frequency is divided by 15 to create 1 Hz (1 second) to be input to the time counter. -
Page 12: Notes On Use
CHAPTER 1 OUTLINE OF µ PD4992 1.7 Notes on Use (1) Be sure to stop the clock (by means of CLK stop) before writing time data. For details, refer to 3.1 Time Setting. (2) To change the hour mode between 12-hour and 24-hour, be sure to rewrite AM/PM and the 10-hour digit, as well as the value of b7. -
Page 13: Chapter 2 Operations
CHAPTER 2 OPERATIONS 2.1 Write Timing Write data to the internal registers in the following procedure. (1) Make CS high. (2) Specify an address value at address pins A through A (3) Make CS low. (4) Make WR low, and then high; the values of data pins D through D will be written to the internal registers at the rising edge of WR. - Page 14 CHAPTER 2 OPERATIONS Figure 2-1. Write Cycle Timing 1 ADDRESS Figure 2-2. Write Cycle Timing 2 (RD = V ADDRESS...
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Page 15: Read Timing
CHAPTER 2 OPERATIONS 2.2 Read Timing Read data from the internal registers in the following procedure. (1) Make CS high. (2) Specify an address value at address pins A through A (3) Make CS low. (4) Make RD low; the value of an internal register will be read to data pins D through D at the falling edge of Table 2-2 and Figures 2-3 and 2-4 indicate the definition of read timing. - Page 16 CHAPTER 2 OPERATIONS Figure 2-4. Read Cycle Timing 2 ADDRESS Data output...
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Page 17: Outline Of Registers
CHAPTER 2 OPERATIONS 2.3 Outline of Registers The registers of the µ PD4992 are allocated as shown in Table 2-3. Addresses 0 through 6 are for time data, and address 7 is a mode register and a control register. Bits b7 and b6 of address 2 are a 12/24H and AM/PM flags, and b7 through b4 of address 3 are a leap year control register and a leap year counter. -
Page 18: Rtc Counter (R/W)
CHAPTER 2 OPERATIONS 2.4 RTC Counter (R/W) Input or output clock data by writing or reading the RTC counter and calendar counter. The data that can be written are as follows: Register Data That Can Be Written 1-second digit 0 through 9 10-second digit 0 through 5 1-minute digit... -
Page 19: 12/24H And Am/Pm Flags (R/W)
CHAPTER 2 OPERATIONS 2.5 12/24H and AM/PM Flags (R/W) The 12/24H flag selects the 12- or 24-hour mode of the hour counter of the µ PD4992. 12/24H flag = 0: 24-hour mode 12/24H flag = 1: 12-hour mode The AM/PM flag indicates either morning or afternoon in the 12-hour mode (when the 12/24H flag = 1). AM/PM flag = 0: Morning (AM 12 hours 00 minutes 00 seconds to AM11 hours 59 minutes 59 seconds) AM/PM flag = 1: Afternoon (PM 12 hours 00 minutes 00 seconds to AM 11 hours 59 minutes 59 seconds) In the 24-hour mode (12/24H flag = 0), the AM/PM flag is always “0”. -
Page 20: Leap Year Control Register And Leap Year Counter (R/W)
CHAPTER 2 OPERATIONS 2.6 Leap Year Control Register and Leap Year Counter (R/W) The leap year control register turns the identification of leap years on and off, and enables or disables writing to the leap year counter. Table 2-5 shows the allocation of the leap year control register. Because the leap year counter does not have to be written again once it has been written, it is usually set to “x0”... -
Page 21: Mode Register (R/W)
CHAPTER 2 OPERATIONS 2.7 Mode Register (R/W) The mode register to specify TP output and the test mode. Table 2-6 lists the functions of the mode register. Table 2-6. Mode Register List Mode TP 2048 Hz output TP 1024 Hz output TP 256 Hz output TP 64 Hz output INT 1/2048 s output... -
Page 22: Tp Output (2) (Interval Pulse Output)
CHAPTER 2 OPERATIONS 2.7.2 TP output (2) (interval pulse output) Pulses are output from the TP pin at intervals of between 1/2048 and 60 seconds when a value between 4 is written to the mode register. The pulse width is 30.5 µ s (refer to Figure 2-6). Figure 2-6. -
Page 23: Control Register
CHAPTER 2 OPERATIONS 2.8 Control Register The control register sets the clock (CLK) of the RTC counter and controls the TP pin when data is written to it. When it is read, the register is used to check the TP, OSC, and BUSY flags. Table 2-7 lists the functions of the control register. Table 2-7. -
Page 24: Write Control Register
CHAPTER 2 OPERATIONS 2.8.1 Write control register Data writing to the control register is to select whether CLK or TP pin is to be controlled depending on the status of b3. (1) When b3 = 0 The CLK stop and CLK reset flags are assigned to b0 and b1, respectively. CLK stop : Stops the 1-second pulse signal to the second digits of the RTC counter to prevent the counter from being incremented. - Page 25 CHAPTER 2 OPERATIONS Figure 2-7. Example of Controlling TP Pin (in INT output mode) (1) Use of INT reset (1) µ INT reset 30.5 s (2) Use of INT reset (2) INT output INT reset INT reset (3) Use of INT stop (1) INT output T = t stop...
- Page 26 CHAPTER 2 OPERATIONS (4) Use of INT stop (2) µ 30.5 s INT output stop stop cleared (5) Use of INT reset and stop INT output stop reset stop cleared (6) Use of TP enable INT output DISABLE ENABLE...
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Page 27: Read Control Register
CHAPTER 2 OPERATIONS 2.8.2 Read control register When the control register is read, the BUSY, OSC, and TP flags can be read. b3 is don’t care. (1) BUSY flag (b0) The BUSY flag is set to ON (b0 = 1) while the internal counter operates (for the ON period, refer to Figure 2-8). - Page 28 [MEMO]...
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Page 29: Chapter 3 Access Procedure
CHAPTER 3 ACCESS PROCEDURE 3.1 Time Setting Because the time counter is updated real-time, it may be set to the wrong value if it is incremented while data is being written to it because of the lapse of time. Therefore, the clock input to the time counter must be stopped before setting the time. -
Page 30: Reading The Time
CHAPTER 3 ACCESS PROCEDURE 3.2 Reading the Time Because the time counter is updated every second, the wrong time data may be read if the time counter is read while it is being incremented. Therefore, read the time by either of the following two methods. <1>... - Page 31 CHAPTER 3 ACCESS PROCEDURE Figure 3-3. Using BUSY Signal to Interrupt CPU Main routine Processing 1 µ Monitor BUSY signal and Access to PD4992 Time read routine issue interrupt every second. (address 0 to 6 Processing 2...
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Page 32: Polling Busy Flag
CHAPTER 3 ACCESS PROCEDURE 3.2.2 Polling BUSY flag The BUSY signal can be also used by polling the BUSY flag. The BUSY flag is assigned to b0 of address 7 (control register). Check (poll) the BUSY flag before reading the time, confirm that it is “0”, and read the time. When the BUSY flag is “1”, the chances are that the time counter is being incremented. -
Page 33: Reading The Time Twice
CHAPTER 3 ACCESS PROCEDURE 3.2.3 Reading the time twice Read the time twice and compare the read values. When both the values coincide, it can be assumed that the time value is correct. To ensure the correct operation, make sure that the rated values of the switching characteristics are satisfied when the time is read. -
Page 34: Limitations On Reading Time
3.2.4 Limitations on reading time With the µ PD4992, clock stop and clock start, which are two of the methods of reading the time with NEC’s 4-bit parallel I/O calendar RTC µ PD4991A, cannot be used (because the time may be delayed). -
Page 35: Setting Tp Output
CHAPTER 3 ACCESS PROCEDURE 3.3 Setting TP Output TP output is set by using the mode register (address 7 ). Because the interval timer is independent of the time counter, it can be independently stopped, resumed, or reset. Figure 3-6 illustrates how to set TP output. Figure 3-6. -
Page 36: Setting When Osc Flag
CHAPTER 3 ACCESS PROCEDURE 3.4 Setting When OSC Flag Is “0” The OSC flag (b1 of address 7 ) is reset to “0” on power application or on stopping oscillation. In this case, the internal status is undefined, but TP output is disabled, regardless of the contents of the internal registers (refer to Figure 3-7). - Page 37 CHAPTER 3 ACCESS PROCEDURE Figure 3-8. Setting when OSC Is “0” Start ← 0F Note TP output control/ Address 7 to BF TP output select (TP = DISABLE, INT reset/stop) Note 1 ← *2 Address 7 CLK reset (*: don't care) OSC flag = 1? Note 1 ←...
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Page 39: Chapter 4 Electrical Specifications And Interface
CHAPTER 4 ELECTRICAL SPECIFICATIONS AND INTERFACE 4.1 Crystal Oscillation Circuit The µ PD4992 uses an oscillation circuit that consists of a single-stage CMOS inverter, feedback resistor R , and oscillation stabilization resistor R Figure 4-1 shows the equivalent circuit of the oscillation circuit. The oscillation frequency of this circuit is determined by external load capacitances C and C , and crystal resonator. -
Page 40: Oscillation Characteristics And Accuracy
CHAPTER 4 ELECTRICAL SPECIFICATIONS AND INTERFACE 4.2 Oscillation Characteristics and Accuracy The accuracy of the RTC function of the µ PD4992 is determined by the accuracy of the oscillation frequency. The oscillation frequency is affected by the load capacitance and temperature. 4.2.1 Dependency on load capacitance Figure 4-2 shows a circuit to test the dependency of the oscillation frequency on load capacitance under conditions = +25 °C. - Page 41 CHAPTER 4 ELECTRICAL SPECIFICATIONS AND INTERFACE Figure 4-3. Changes in Frequency When C and C Are Changed at Same Time − 10 − 20 − 30 − 40 − 50 − 60 (pF) Figure 4-4. Changes in Frequency When C Is Changed (C = 18 pF) −...
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Page 42: Dependency On Temperature
CHAPTER 4 ELECTRICAL SPECIFICATIONS AND INTERFACE 4.2.2 Dependency on temperature The oscillation frequency changes with ambient temperature. Figure 4-6 shows the ambient temperature vs. oscillation frequency characteristics. As can be seen, the temperature characteristic curve is of the negative second order with its summit at around 25 °C. -
Page 43: Backup Circuit
CHAPTER 4 ELECTRICAL SPECIFICATIONS AND INTERFACE 4.4 Backup Circuit The µ PD4992 can be backed up by low-capacity batteries because it is a CMOS IC that operates with low current consumption. Figure 4-7 shows an example of backing up the µ PD4992 with a Ni-Cd battery, while Figure 4-8 shows an example of using a super capacitor (high-capacity, electric double layer capacitor). -
Page 44: Power-Fail Circuit
CHAPTER 4 ELECTRICAL SPECIFICATIONS AND INTERFACE 4.5 Power-Fail Circuit While the µ PD4992 is backed up, it is necessary to prohibit external access to the IC by fixing the CS pin to the low level. The power-fail circuit, therefore, must fix CS to the low level if the power supply to the system drops below the operating voltage of the CPU (e.g., 4.5 V or less), and keep CS low until the CPU operates again (refer to Figure... - Page 45 [MEMO]...
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- Page 47 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.