Epson S1C6200 Manuals

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Epson S1C6200 Core Cpu Manual (98 pages)

Epson CMOS 4-Nit Single Chip Microcomputer Core CPU Manual

Brand: Epson | Category: Computer Hardware | Size: 0.57 MB

Table of Contents
5
1 Description

7
2 Memory and Operations

9
- Program Memory (ROM)
  9
  - Program Counter Block
    10
  - Flags
    10
  - Jump Instructions
    11
  - PSET with Jump Instructions
    11
  - Call Instructions
    11
  - PSET Instruction
    12
  - CALZ Instruction
    12
  - RET and RETS Instructions
    13
  - Stack Considerations for Call Instructions
    13
- Data Memory
  14
  - Data Memory Addressing
    14
- ALU (Arithmetic Logic Unit) and Registers
  16
  - D (Decimal) Flag and Decimal Operations
    16
  - A and B Registers
    17
- Timing Generator
  17
  - HALT and SLP (Sleep) Modes
    17
- Interrupts
  18
  - Interrupt Vectors
    18
  - I (Interrupt) Flag
    18
  - Operation During Interrupt Generation
    18
  - Initial Reset
    21
3 Instruction Set

22
- Nstruction Et
  
  22
- Instruction Indices
  22
  - By Function
    23
  - In Alphabetical Order
    26
  - By Operation Code
    29
- Operands
  32
- Flags
  32
- Instruction Types
  33
- Instruction Descriptions
  33
  - Acpx MX,R Add with Carry R-Register to M(X), Increment X by
    34
  - And R,I
    39
  - Logical and Immediate Data I with R-Register
    39
  - And R,Q
    39
  - Logical and Q-Register with R-Register
    39
  - Cp R,I
    41
  - Compare Immediate Data I with R-Register
    41
  - Cp R,Q
    41
  - Compare Q-Register with R-Register
    41
  - Cp Xh,I
    42
  - Compare Immediate Data I with Xh
    42
  - Cp Xl,I
    42
  - Compare Immediate Data I with Xl
    42
  - Cp Yh,I
    43
  - Compare Immediate Data I with Yh
    43
  - Cp Yl,I
    43
  - Compare Immediate Data I with Yl
    43
  - Disable Interrupts
    45
  - Enable Interrupts
    45
  - Inc Sp
    48
  - Increment Stack Pointer by
    48
  - Inc X
    48
  - Increment X-Register by
    48
  - Inc y
    49
  - Increment Y-Register by
    49
  - Indirect Jump Using Registers a and B
    49
- Lbpx MX,E Load Immediate Data E to Memory, and Increment X by
  52
- Ld A,Mn
  53
- Load Memory into A-Register
  53
- Ld B,Mn
  53
- Load Memory into B-Register
  53
- No Operation for 5 Clock Cycles
  67
- No Operation for 7 Clock Cycles
  67
- Or R,Q
  69
- Logical or Q-Register with R-Register
  69
- Pop F
  69
- Pop Stack Data into Flags
  69
- Pop Xl
  71
- Pop Stack Data into Xl
  71
- Pop Xp
  71
- Pop Stack Data into Xp
  71
- Pop Yh
  72
- Pop Stack Data into Yh
  72
- Pop Yl
  72
- Pop Stack Data into Yl
  72
- Push Xh
  75
- Push Xh Onto Stack
  75
- Push Xl
  75
- Push Xl Onto Stack
  75
- Push Xp
  76
- Push Xp Onto Stack
  76
- Push Yh
  76
- Push Yh Onto Stack
  76
- Push Yl
  77
- Push Yl Onto Stack
  77
- Push Yp
  77
- Push Yp Onto Stack
  77
- Reset Carry Flag
  78
- Reset Decimal Flag
  78
- Return from Subroutine
  79
- Retd E
  79
- Load Immediate Data E to Memory, and Increment X by 2, then Return
  79
- Sbc R,Q
  83
- Subtract with Carry Q-Register from R-Register
  83
- Set Carry Flag
  83
- Set Decimal Flag
  85
- Set F,I
  85
- Set Flags Using Immediate Data I
  85
- Set Zero Flag
  87
- Xor R,I
  87
- Exclusive-Or Immediate Data I with R-Register
  87
Appendix A. S1C6200A (a Dvanced S1C6200) C Ore Cpu

90
- Instruction
  92
- B. I Nstruction I Ndex
  93
Appendix

90
- S1C6200A (Advanced S1C6200) Core Cpu
  90

Epson S1C6200 Core Cpu Manual (97 pages)

Core Cpu CMOS 4-BIT SINGLE CHIP MICROCOMPUTER

Brand: Epson | Category: Computer Hardware | Size: 0.56 MB

Table of Contents
5
1 Description

7
2 Memory and Operations

9
- Program Memory (ROM)
  9
  - Program Counter Block
    10
  - Flags
    10
  - Jump Instructions
    11
  - PSET with Jump Instructions
    11
  - Call Instructions
    11
  - PSET Instruction
    12
  - CALZ Instruction
    12
  - RET and RETS Instructions
    13
  - Stack Considerations for Call Instructions
    13
- Data Memory
  14
  - Data Memory Addressing
    14
- ALU (Arithmetic Logic Unit) and Registers
  16
  - D (Decimal) Flag and Decimal Operations
    16
  - A and B Registers
    17
- Timing Generator
  17
  - HALT and SLP (Sleep) Modes
    17
- Interrupts
  18
  - Interrupt Vectors
    18
  - I (Interrupt) Flag
    18
  - Operation During Interrupt Generation
    18
  - Initial Reset
    21
3 Instruction Set

22
- Nstruction Et
  
  22
- Instruction Indices
  22
  - By Function
    23
  - In Alphabetical Order
    26
  - By Operation Code
    29
- Operands
  32
- Flags
  32
- Instruction Types
  33
- Instruction Descriptions
  33
  - Acpx MX,R Add with Carry R-Register to M(X), Increment X by
    34
  - And R,I
    39
  - Logical and Immediate Data I with R-Register
    39
  - And R,Q
    39
  - Logical and Q-Register with R-Register
    39
  - Cp R,I
    41
  - Compare Immediate Data I with R-Register
    41
  - Cp R,Q
    41
  - Compare Q-Register with R-Register
    41
  - Cp Xh,I
    42
  - Compare Immediate Data I with Xh
    42
  - Cp Xl,I
    42
  - Compare Immediate Data I with Xl
    42
  - Cp Yh,I
    43
  - Compare Immediate Data I with Yh
    43
  - Cp Yl,I
    43
  - Compare Immediate Data I with Yl
    43
  - Disable Interrupts
    45
  - Enable Interrupts
    45
  - Inc Sp
    48
  - Increment Stack Pointer by
    48
  - Inc X
    48
  - Increment X-Register by
    48
  - Inc y
    49
  - Increment Y-Register by
    49
  - Indirect Jump Using Registers a and B
    49
- Lbpx MX,E Load Immediate Data E to Memory, and Increment X by
  52
- Ld A,Mn
  53
- Load Memory into A-Register
  53
- Ld B,Mn
  53
- Load Memory into B-Register
  53
- No Operation for 5 Clock Cycles
  67
- No Operation for 7 Clock Cycles
  67
- Or R,Q
  69
- Logical or Q-Register with R-Register
  69
- Pop F
  69
- Pop Stack Data into Flags
  69
- Pop Xl
  71
- Pop Stack Data into Xl
  71
- Pop Xp
  71
- Pop Stack Data into Xp
  71
- Pop Yh
  72
- Pop Stack Data into Yh
  72
- Pop Yl
  72
- Pop Stack Data into Yl
  72
- Push Xh
  75
- Push Xh Onto Stack
  75
- Push Xl
  75
- Push Xl Onto Stack
  75
- Push Xp
  76
- Push Xp Onto Stack
  76
- Push Yh
  76
- Push Yh Onto Stack
  76
- Push Yl
  77
- Push Yl Onto Stack
  77
- Push Yp
  77
- Push Yp Onto Stack
  77
- Reset Carry Flag
  78
- Reset Decimal Flag
  78
- Return from Subroutine
  79
- Retd E
  79
- Load Immediate Data E to Memory, and Increment X by 2, then Return
  79
- Sbc R,Q
  83
- Subtract with Carry Q-Register from R-Register
  83
- Set Carry Flag
  83
- Set Decimal Flag
  85
- Set F,I
  85
- Set Flags Using Immediate Data I
  85
- Set Zero Flag
  87
- Xor R,I
  87
- Exclusive-Or Immediate Data I with R-Register
  87
Appendix A. S1C6200A (a Dvanced S1C6200) C Ore Cpu

90
- Instruction
  92
- B. I Nstruction I Ndex
  93
Appendix

90
- S1C6200A (Advanced S1C6200) Core Cpu
  90

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Epson S1C6200 Core Cpu Manual (98 pages)

Table of Contents

1 Description

2 Memory and Operations

3 Instruction Set

Nstruction Et

Appendix A. S1C6200A (a Dvanced S1C6200) C Ore Cpu

Appendix