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Fujitsu MB90480 Series manual available for free PDF download: Hardware Manual
Fujitsu MB90480 Series Hardware Manual (688 pages)
F2MC-16LX 16-BIT MICROCONTROLLER
Brand:
Fujitsu
| Category:
Microcontrollers
| Size: 11.16 MB
Table of Contents
Table of Contents
11
Chapter 1 Overview of Mb90480/485 Series
23
Features of MB90480/485 Series
24
Block Diagram of MB90480/485 Series
28
Package Dimensions
29
Pin Assignment
31
Pin Functions
33
I/O Circuit Type
40
Handling the Device
43
Chapter 2 Cpu
45
Overview of CPU Specifications
46
Memory Space
47
CPU Registers
51
Accumulator (A)
53
User Stack Pointer (USP) and System Stack Pointer (SSP)
54
Processor Status (PS)
55
Program Counter (PC)
58
Program Counter Bank Register (PCB)
59
Direct Page Register (DPR)
60
General-Purpose Register (Register Bank)
61
Prefix Codes
62
Chapter 3 Interrupt
65
Overview of Interrupt
66
Interrupt Factor and Interrupt Vector
68
Interrupt Control Register and Peripheral Function
71
Interrupt Control Register (ICR00 to ICR15)
72
Hardware Interrupt
75
Hardware Interrupt Operation
78
Flow of Hardware Interrupt Operation
80
Procedure for Using Hardware Interrupt
81
Multiple Interrupts
83
Hardware Interrupt Processing Time
85
Software Interrupt
87
Interrupt by Μdmac
89
DMA Descriptor
92
Individual Registers of DMA Descriptor
94
Μdmac Processing Procedure
97
Μdmac Processing Time
98
Interrupt by Extended Intelligent I/O Service (EI OS)
100
EI 2 os Descriptor (ISD)
102
Each Register of EI 2 os Descriptor (ISD)
104
Operation of EI 2 os
107
Procedure for Use of EI
108
Processing Time of the Extended Intelligent I/O Service (EI 2 OS)
109
Exception Processing Interrupt
111
Stack Operation of Interrupt Processing
112
Sample Program of Interrupt Processing
114
Delay Interrupt Generation Module
115
Operation of Delay Interrupt Generation Module
116
Chapter 4 Reset
117
Overview of Reset
118
Reset Factors and Oscillation Stabilization Wait Time
120
External-Reset Pin
122
Resetting
123
Reset-Factor Bits
125
Condition of Pins as Result of Reset
127
Chapter 5 Clocks
129
Overview of Clocks
130
Block Diagram of Clock Generator
132
Clock Selection Register (CKSCR) and PLL Output Selection Register (PLLOS)
134
Clock Modes
139
Oscillation Stabilization Wait Time
143
Connecting Oscillator to External Clock
144
Chapter 6 Low-Power Consumption Mode
145
Overview of Low-Power Consumption Mode
146
Block Diagram of Low-Power Consumption Control Circuit
148
Low-Power Consumption Mode Control Register (LPMCR)
150
CPU Intermittent Operation Mode
153
Standby Mode
154
Sleep Mode
155
Timebase Timer Mode
157
Watch Mode
159
Stop Mode
161
State Transition Diagram
163
Pin State in Standby Mode, Hold, and Reset
165
Caution on Using Low-Power Consumption Mode
170
Chapter 7 Mode Setting
175
Mode Setting
176
Mode Pins (MD2 to MD0)
177
Mode Data
178
External Memory Access
182
Automatic Ready Function Selection Register (ARSR)
184
External Address Output Control Register (HACR)
186
Bus Control Signal Selection Register (EPCR)
187
Operation of each Mode for Mode Setting
189
External Memory Access Control Signals
190
Ready Function
193
Hold Function
196
Chapter 8 I/O Port
199
Functions of I/O Port
200
Registers for I/O Port
201
Port Registers (PDR0 to PDRA)
202
Port Direction Registers (DDR0 to DDRA)
203
Other Registers
205
Chapter 9 Timebase Timer
207
Overview of Timebase Timer
208
Timebase Timer Configuration
210
Timebase Timer Control Register (TBTC)
212
Timebase Timer Interrupt
214
Timebase Timer Operation
215
Notes on Using Timebase Timer
218
Sample Programs of Timebase Timer
219
Chapter 10 Watchdog Timer
221
Overview of Watchdog Timer
222
Watchdog Timer Control Register (WDTC)
223
Watchdog Timer Configuration
225
Watchdog Timer Operation
227
Notes on Using Watchdog Timer
229
Sample Programs of Watchdog Timer
230
Chapter 11 Watch Timer
231
Overview of Watch Timer
232
Watch Timer Configuration
233
Watch Timer Control Register (WTC)
234
Watch Timer Operation
236
Chapter 12 16-Bit Input/Output Timer
239
Overview of 16-Bit Input/Output Timer
240
Configuration of 16-Bit Input/Output Timer
241
Configuration and Function of 16-Bit Input/Output Timer Register
245
Free-Running Timer
246
Output Compare
251
Input Capture
255
Interrupt of 16-Bit Input/Output Timer
257
16-Bit Input/Output Timer Operation
259
Operation of Free-Running Timer
260
Operation of Output Compare
262
Operation of Input Capture
264
Free-Running Timer Timing
265
Output Compare Timing
266
Timing of Input Capture
267
Program Example of 16-Bit Input/Output Timer
268
Chapter 13 8/16-Bit Up/Down Counter/Timer
281
Overview of 8/16-Bit Up/Down Counter Timer
282
Configuration of 8/16-Bit Up/Down Counter/Timer
283
Configuration and Functions of Registers for 8/16-Bit Up/Down Counter/Timer
286
Counter Control Register (Ch.0) Upper (CCRH0)
287
Counter Control Register (Ch.1) Upper (CCRH1)
289
Counter Control Register (Ch.0/Ch.1) Lower (CCRL0/CCRL1)
291
Counter Status Register 0/1 (CSR0/CSR1)
293
Up/Down Count Register (Ch.0/Ch.1) (UDCR0/UDCR1)
295
Reload/Compare Register (Ch.0/Ch.1) (RCR0/RCR1)
296
Interrupt of 8/16-Bit Up/Down Counter/Timer
297
8/16-Bit Up/Down Counter/Timer Operation
299
Reload/Compare Function
302
Writing Data to Up/Down Count Register (UDCR)
305
Program Example of 8/16-Bit Up/Down Counter/Timer
307
Chapter 14 16-Bit Reload Timer
313
Overview of 16-Bit Reload Timer
314
Configuration and Functions of 16-Bit Reload Timer Registers
318
Timer Control Status Register (TMCSR)
319
16-Bit Timer Register (TMR)/16-Bit Reload Register (TMRLR)
323
Interrupt of 16-Bit Reload Timer
325
Operations of the 16-Bit Reload Timer
326
State Transitions During Count Operation
327
Operations of Internal Clock Mode (Reload Mode)
328
Internal Clock Mode (One-Shot Mode)
330
Event Count Mode
332
Program Example of 16-Bit Reload Timer
334
Chapter 15 8/16-Bit Ppg Timer
339
Overview of 8/16-Bit PPG Timer
340
Configuration of 8/16-Bit PPG Timer
341
Configuration and Functions of 8/16-Bit PPG Timer Registers
344
PPG0/2/4 Operation Mode Control Register (PPGC0/PPGC2/PPGC4)
345
PPG1/3/5 Operation Mode Control Register (PPGC1/PPGC3/PPGC5)
347
PPG0 to PPG5 Output Control Registers (PPG01, PPG23, PPG45)
350
Reload Registers (PRLL0 to PRLL5, PRLH0 to PRLH5)
352
Interrupt of 8/16-Bit PPG Timer
353
Operations of 8/16-Bit PPG Timer
355
Program Example of 8/16-Bit PPG Timer
360
Chapter 16 Dtp/External Interrupts
363
Overview of Dtp/External Interrupt Unit
364
Configuration and Functions of Dtp/External Interrupt Unit Registers
366
Dtp/External Interrupt
368
Operations of Dtp/External Interrupt Unit
370
Precautions on Use of Dtp/External Interrupt Unit
372
Program Example of Dtp/External Interrupt
374
Chapter 17 8/10-Bit A/D Converter
377
Overview of 8/10-Bit A/D Converter
378
Configuration of 8/10-Bit A/D Converter
379
Configuration and Functions of 8/10-Bit A/D Converter Registers
381
Control Status Register 1 (ADCS1)
382
Control Status Register 2 (ADCS2)
385
Data Registers (ADCR2 and ADCR1)
388
Interrupt of 8/10-Bit A/D Converter
389
Operations of 8/10-Bit A/D Converter
390
Example of Μdmac Start in Single Mode
392
Example of Μdmac Start in Continuous Mode
394
Example of Μdmac Start in Stop Mode
396
Conversion Data Protection Function of 8/10-Bit A/D Converter
398
Precautions on Use of the 8/10-Bit A/D Converter
400
Program Example of 8/10-Bit A/D Converter
401
Chapter 18 Expanded I/O Serial Interface
407
Overview of Expanded I/O Serial Interface
408
Configuration of Expanded I/O Serial Interface
409
Configuration and Functions of Expanded I/O Serial Interface Registers
411
Serial Mode Control Status Register 0/1 (SMCS0/SMCS1)
412
Serial Data Register 0/1 (SDR0/SDR1)
416
Communication Prescaler Control Register0/1 (SDCR0/SDCR1)
417
Interrupt of Expanded I/O Serial Interface
418
Operation of Expanded I/O Serial Interface
419
Shift Clock Modes
420
Operational States of Serial I/O Units
421
Start/Stop Timing and Input/Output Timing of Shift Operation
423
Interrupt Function
425
Program Example of Expanded I/O Serial Interface
426
Chapter 19 Uart
429
Overview of the UART
430
Configuration of UART
431
Configuration and Functions of UART Registers
433
Serial Mode Register (SMR)
434
Serial Control Register (SCR)
436
Serial Input/Output Register (SIDR/SODR)
438
Serial Status Register (SSR)
439
Communication Prescaler Control Register (CDCR)
441
Interrupt of UART
443
UART Operations
445
Operation in Asynchronous Mode (Operation Modes 0 and 1)
449
Operation in Synchronous Mode (Operation Mode 2)
452
Two-Way Communication Function (Normal Mode)
454
Master/Slave Communication Function (Multiprocessor Mode)
456
Precautions on Use of the UART
459
Program Example of UART
460
Chapter 20 Chip Selection Facility
467
Overview of Chip Selection Facility
468
Configuration of Chip Selection Facility
469
Configuration and Functions of Chip Selection Facility Registers
471
Chip Select Area MASK Register (Cmrx)
472
Chip Selection Area Register (Carx)
473
Chip Selection Control Register (CSCR)
474
Chip Selection Active Level Register (CALR)
475
Operation of the Chip Selection Facility
476
Chapter 21 Address Match Detection Function
479
Overview of Address Match Detection Function
480
Block Diagram of Address Match Detection Function
481
Configuration of Registers for Address Match Detection Function
482
Program Address Detection Control Status Register (PACSR)
483
Program Address Detection Registers (PADR0, PADR1)
485
Explanation of Operation of Address Match Detection Function
487
Example of Using Address Match Detection Function
488
Program Example of Address Match Detection Function
493
Chapter 22 Rom Mirror Function Selection Module
495
Overview of ROM Mirror Function Selection Module
496
ROM Mirror Function Selection Register (ROMM)
497
Chapter 23 2M/3M Bit Flash Memory
499
Overview of 2M/3M Bit Flash Memory
500
Sector Configuration of 2M/3M Bit Flash Memory
501
Flash Memory Control Status Register (FMCS)
502
Method for Starting the Flash Memory's Automatic Algorithm
508
Verifying the Execution State of the Automatic Algorithm
509
Data Polling Flag (DQ7)
511
Toggle Bit Flag (DQ6)
513
Timing Limit Excess Flag (DQ5)
514
Sector Erase Timer Flag (DQ3)
515
Flash Memory Write/Erase Operations
516
Setting the Flash Memory to Read/Reset State
517
Writing Data to Flash Memory
518
Erasing All Data in the Flash Memory (Chip Erase)
520
Erasing Arbitrary Data in Flash Memory (Sector Erase)
521
Suspending Sector Erasure for the Flash Memory
523
Resuming the Sector Erasure of Flash Memory
524
Flash Security Function
525
Chapter 24 Examples of Mb90F481B/Mb90F482B/Mb90F488B/Mb90F489B Serial Programming Connection
527
Basic Configuration of Serial Programming Connection with MB90F481B/MB90F482B/MB90F488B/MB90F489B
528
Example of Connection in Single-Chip Mode (When Using the User Power Supply)
532
Example of Minimum Connection with Flash Microcontroller Programmer (When Using the User Power Supply)
534
Chapter 25 Pwc Timer (Only Mb90485 Series)
537
Overview of PWC Timer
538
Configuration of PWC Timer
539
Configuration and Functions of PWC Timer Registers
541
PWC Control/Status Register (PWCSR0 to PWCSR2)
542
PWC Data Buffer Register (PWCR0 to PWCR2)
547
Divide Ratio Control Register (DIVR0 to DIVR2)
548
Interrupt of PWC Timer
549
Operations of PWC Timer
551
Operations of the Timer Function
552
Operations of the Pulse Width Measurement Function
553
Selection of Count Clock and Operation Mode
555
Start and Stop of Timer/Pulse Width Measurement
557
Timer Mode Operation
559
Operation in Pulse Width Measurement Mode
562
Notes on PWC Timer Usage
568
CHAPTER 26 Μpg TIMER (ONLY MB90485 SERIES)
571
Overview and Configuration of Μpg Timer
572
Configuration and Functions of Μpg Timer Registers
574
Timing Chart of Μpg Timer
576
Chapter 27 I 2 C Interface (Only Mb90485 Series)
577
Overview of I
578
Interface
578
Configuration of I
579
Interface
579
Configuration and Functions of I C Interface Registers
581
Bus Status Register (IBSR)
582
Bus Control Register (IBCR)
584
Clock Control Register (ICCR)
590
Address Register (IADR)
592
Data Register (IDAR)
593
Interrupt of I 2 C Interface
594
I 2 C Interface Operation
596
Appendix
599
APPENDIX A Memory Map
600
APPENDIX B I/O Map
603
APPENDIX C Interrupt Source, Interrupt Vector, and Interrupt Control Register
611
APPENDIX D Instructions
613
Instruction Types
614
D.1 Instruction Types
614
Addressing
615
D.2 Addressing
615
Direct Addressing
617
D.3 Direct Addressing
617
Indirect Addressing
622
D.4 Indirect Addressing
622
Execution Cycle Count
628
Effective Address Field
631
How to Read the Instruction List
632
MC-16LX Instruction List
635
Instruction Map
649
D.9 Instruction Map
649
Index
671
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