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Fujitsu MB90895 Series Microcontroller Manuals
Manuals and User Guides for Fujitsu MB90895 Series Microcontroller. We have
1
Fujitsu MB90895 Series Microcontroller manual available for free PDF download: Hardware Manual
Fujitsu MB90895 Series Hardware Manual (710 pages)
16 Bit, Controller Manual
Brand:
Fujitsu
| Category:
Microcontrollers
| Size: 12.52 MB
Table of Contents
Table of Contents
11
Chapter 1 Overview
19
Features of the MB90895 Series
20
Product Lineup for MB90895 Series
22
Block Diagram of MB90895 Series
25
Pin Assignment
26
Package Dimensions
27
Pin Description
28
I/O Circuit
31
Chapter 2 Handling Devices
33
Precautions When Handling Devices
34
Chapter 3 Cpu
37
Memory Space
38
Mapping of and Access to Memory Space
40
Memory Map
42
Addressing
43
Linear Addressing
44
Bank Addressing
45
Allocation of Multi-Byte Data in Memory
47
Dedicated Registers
49
Dedicated Registers and General-Purpose Register
51
Accumulator (A)
52
Stack Pointer (USP, SSP)
55
Processor Status (PS)
58
Program Counter (PC)
63
Direct Page Register (DPR)
64
Bank Register (PCB, DTB, USB, SSB, and ADB)
65
General-Purpose Register
66
Prefix Code
68
Bank Select Prefix (PCB, DTB, ADB, and SPB)
69
Common Register Bank Prefix (CMR)
71
Flag Change Inhibit Prefix (NCC)
72
Restrictions on Prefix Code
73
Interrupt
75
Interrupt Factor and Interrupt Vector
77
Interrupt Control Registers and Peripherals
80
Interrupt Control Register (ICR00 to ICR15)
82
Function of Interrupt Control Register
84
Hardware Interrupt
87
Operation of Hardware Interrupt
90
Procedure for Use of Hardware Interrupt
92
Multiple Interrupts
93
Software Interrupt
95
Interrupts by Extended Intelligent I/O Service (EI 2 OS)
96
EI os Descriptor (ISD)
98
Each Register of EI 2 os Descriptor (ISD)
100
Operation of EI 2 os
103
Procedure for Use of EI 2 os
104
EI 2 os Processing Time
105
Exception Processing Interrupt
107
Time Required to Start Interrupt Processing
108
Stack Operation for Interrupt Processing
110
Program Example of Interrupt Processing
111
Reset
114
Reset Factors and Oscillation Stabilization Wait Times
116
External Reset Pin
118
Reset Operation
119
Reset Factor Bit
121
State of each Pin at Reset
124
Clock
125
Block Diagram of Clock Generation Section
128
Register in Clock Generation Section
130
Clock Select Register (CKSCR)
131
Pll/Subclock Control Register (PSCCR)
134
Clock Mode
136
Oscillation Stabilization Wait Time
140
Connection of Oscillator and External Clock
141
Low-Power Consumption Mode
142
Block Diagram of Low-Power Consumption Circuit
145
Registers for Setting Low-Power Consumption Modes
147
Low-Power Consumption Mode Control Register (LPMCR)
148
CPU Intermittent Operation Mode
151
Standby Mode
152
State Transition in Standby Mode
163
Pin State in Standby Mode, at Reset
164
Precautions When Using Low-Power Consumption Mode
165
CPU Mode
169
Mode Pins (MD2 to MD0)
170
Mode Data
172
Memory Access Mode
174
Operations for Selecting Memory Access Mode
175
Chapter 4 I/O Port
177
Overview of I/O Ports
178
Registers of I/O Port and Assignment of Pins Serving as External Bus
179
Port 1
180
Registers for Port 1 (PDR1, DDR1)
182
Operation of Port 1
183
Port2
185
Registers for Port 2 (PDR2, DDR2)
188
Operation of Port 2
189
Port 3
191
Registers for Port 3 (PDR3, DDR3)
193
Operation of Port 3
194
Port 4
196
Registers for Port 4 (PDR4, DDR4)
198
Operation of Port 4
199
Port 5
201
Registers for Port 5 (PDR5, DDR5, ADER)
204
Operation of Port 5
206
Port Input Level Select Register
208
CHAPTER 5 Timebase Timer
209
Overview of Timebase Timer
210
Block Diagram of Timebase Timer
212
Configuration of Timebase Timer
214
Timebase Timer Control Register (TBTC)
215
Interrupt of Timebase Timer
217
Explanation of Operations of Timebase Timer Functions
218
Precautions When Using Timebase Timer
222
Program Example of Timebase Timer
223
CHAPTER 6 Watchdog Timer
225
Overview of Watchdog Timer
226
Configuration of Watchdog Timer
227
Watchdog Timer Registers
229
Watchdog Timer Control Register (WDTC)
230
Explanation of Operations of Watchdog Timer Functions
232
Precautions When Using Watchdog Timer
235
Program Examples of Watchdog Timer
236
CHAPTER 7 16-Bit I/O Timer
237
Overview of 16-Bit Input/Output Timer
238
Block Diagram of 16-Bit Input/Output Timer
239
Block Diagram of 16-Bit Free-Run Timer
240
Block Diagram of Input Capture
242
Configuration of 16-Bit Input/Output Timer
244
Timer Counter Control Status Register (TCCS)
247
Timer Counter Data Register (TCDT)
249
Input Capture Control Status Registers (ICS01, ICS23)
251
Input Capture Data Registers (IPCP0 to IPCP3)
253
Interrupts of 16-Bit Input/Output Timer
254
Explanation of Operation of 16-Bit Free-Run Timer
255
Explanation of Operation of Input Capture
257
Precautions When Using 16-Bit Input/Output Timer
260
Program Example of 16-Bit Input/Output Timer
261
CHAPTER 8 16-Bit Reload Timer
263
Overview of 16-Bit Reload Timer
264
Block Diagram of 16-Bit Reload Timer
267
Configuration of 16-Bit Reload Timer
270
Timer Control Status Registers (High) (TMCSR0: H, TMCSR1: H)
273
Timer Control Status Registers (High) (TMCSR0: H, TMCSR1: H)
275
16-Bit Timer Registers (TMR0, TMR1)
277
16-Bit Reload Registers (TMRLR0, TMRLR1)
278
Interrupts of 16-Bit Reload Timer
279
Explanation of Operation of 16-Bit Reload Timer
280
Operation in Internal Clock Mode
282
Operation in Event Count Mode
287
Precautions When Using 16-Bit Reload Timer
290
Program Example of 16-Bit Reload Timer
291
CHAPTER 9 Watch Timer
295
Overview of Watch Timer
296
Block Diagram of Watch Timer
298
Configuration of Watch Timer
300
Watch Timer Control Register (WTC)
301
Watch Timer Interrupt
303
Explanation of Operation of Watch Timer
304
Program Example of Watch Timer
306
CHAPTER 10 8/16-Bit PPG Timer
307
Overview of 8-/16-Bit PPG Timer
308
Block Diagram of 8-/16-Bit PPG Timer
311
Block Diagram for 8-/16-Bit PPG Timer 0
312
Block Diagram of 8-/16-Bit PPG Timer 1
314
Configuration of 8-/16-Bit PPG Timer
317
PPG0 Operation Mode Control Register (PPGC0)
319
PPG1 Operation Mode Control Register (PPGC1)
321
PPG0/1 Count Clock Select Register (PPG01)
323
PPG Reload Registers (PRLL0/PRLH0, PRLL1/PRLH1)
325
Interrupts of 8-/16-Bit PPG Timer
326
Explanation of Operation of 8-/16-Bit PPG Timer
328
8-Bit PPG Output 2-Channel Independent Operation Mode
329
16-Bit PPG Output Mode
331
8-Bit PPG Output Mode
334
Precautions When Using 8-/16-Bit PPG Timer
337
CHAPTER 11 Delayed Interrupt Generation Module
339
Overview of Delayed Interrupt Generation Module
340
Block Diagram of Delayed Interrupt Generation Module
341
Configuration of Delayed Interrupt Generation Module
342
Delayed Interrupt Request Generate/Cancel Register (DIRR)
343
Explanation of Operation of Delayed Interrupt Generation Module
344
Precautions When Using Delayed Interrupt Generation Module
345
Program Example of Delayed Interrupt Generation Module
346
CHAPTER 12 Dtp/External Interrupt
347
Overview of Dtp/External Interrupt
348
Block Diagram of Dtp/External Interrupt
349
Configuration of Dtp/External Interrupt
351
Dtp/External Interrupt Factor Register (EIRR)
352
Dtp/External Interrupt Enable Register (ENIR)
353
Detection Level Setting Register (ELVR) (High)
354
Detection Level Setting Register (ELVR) (Low)
355
Explanation of Operation of Dtp/External Interrupt
356
External Interrupt Function
359
DTP Function
360
Precautions When Using Dtp/External Interrupt
361
Program Example of Dtp/External Interrupt Function
363
CHAPTER 13 8/10-Bit A/D Converter
367
Overview of 8-/10-Bit A/D Converter
368
Block Diagram of 8-/10-Bit A/D Converter
369
Configuration of 8-/10-Bit A/D Converter
372
A/D Control Status Register (High) (ADCS: H)
374
A/D Control Status Register (Low) (ADCS: L)
377
A/D Data Register (High) (ADCR: H)
380
A/D Data Register (Low) (ADCR: L)
382
Analog Input Enable Register (ADER)
383
Interrupt of 8-/10-Bit A/D Converter
385
Explanation of Operation of 8-/10-Bit A/D Converter
386
Single-Shot Conversion Mode
387
Continuous Conversion Mode
389
Pause-Conversion Mode
391
Conversion Using EI 2 os Function
393
A/D-Converted Data Protection Function
394
Precautions When Using 8-/10-Bit A/D Converter
397
Chapter 14 Uart0
399
Overview of UART0
400
Block Diagram of UART0
402
Configuration of UART0
405
Serial Control Register 0 (SCR0)
407
Serial Mode Register 0 (SMR0)
409
Serial Status Register 0 (SSR0)
411
Serial Input Data Register 0 (SIDR0) and Serial Output Data Register 0 (SODR0)
413
Communication Prescaler Control Register 0 (CDCR0)
415
Serial Edge Select Register 0 (SES0)
416
Interrupt of UART0
417
Generation of Receive Interrupt and Timing of Flag Set
419
Generation of Transmit Interrupt and Timing of Flag Set
421
UART0 Baud Rate
423
Baud Rate by Dedicated Baud Rate Generator
425
Baud Rate by Internal Timer (16-Bit Reload Timer)
428
Baud Rate by External Clock
430
Explanation of Operation of UART0
431
Operation in Asynchronous Mode (Operation Mode 0 or 1)
433
Operation at Clock Synchronous Mode (Operating Mode 2)
437
Bidirectional Communication Function (Operation Modes 0 and 2)
440
Master/Slave Type Communication Function (Multi Processor Mode)
442
Precautions When Using UART0
445
Chapter 15 Uart1
447
Overview of UART1
448
Block Diagram of UART1
450
Configuration of UART1
453
Serial Control Register 1 (SCR1)
455
Serial Mode Register 1 (SMR1)
457
Serial Status Register 1 (SSR1)
459
Serial Input Data Register 1 (SIDR1) and Serial Output Data Register 1 (SODR1)
462
Communication Prescaler Control Register 1 (CDCR1)
464
Interrupt of UART1
466
Generation of Receive Interrupt and Timing of Flag Set
468
Generation of Transmit Interrupt and Timing of Flag Set
470
UART1 Baud Rate
471
Baud Rate by Dedicated Baud Rate Generator
473
Baud Rate by Internal Timer (16-Bit Reload Timer)
476
Baud Rate by External Clock
478
Explanation of Operation of UART1
479
Operation in Asynchronous Mode (Operation Mode 0 or 1)
481
Operation in Clock Synchronous Mode (Operation Mode 2)
485
Bidirectional Communication Function (Operation Modes 0 and 2)
487
Master/Slave Type Communication Function (Multiprocessor Mode)
489
Precautions When Using UART1
492
Program Example for UART1
493
CHAPTER 16 CAN Controller
495
Overview of CAN Controller
496
Block Diagram of CAN Controller
497
Configuration of CAN Controller
500
Control Status Register (High) (CSR: H)
504
Control Status Register (Low) (CSR: L)
506
Last Event Indication Register (LEIR)
509
Receive/Transmit Error Counter (RTEC)
511
Bit Timing Register (BTR)
513
Message Buffer Validating Register (BVALR)
517
IDE Register (IDER)
519
Transmit Request Register (TREQR)
521
Transmit RTR Register (TRTRR)
523
Remote Frame Receive Waiting Register (RFWTR)
525
Transmission Cancel Register (TCANR)
527
Transmit Complete Register (TCR)
529
Transmit Complete Interrupt Enable Register (TIER)
531
Receive Complete Register (RCR)
533
Receive RTR Register (RRTRR)
535
Receive Overrun Register (ROVRR)
537
Receive Complete Interrupt Enable Register (RIER)
539
Acceptance Mask Select Register (AMSR)
541
Acceptance Mask Select Register (AMR)
543
Message Buffers
545
ID Register (Idrx, X = 7 to 0)
546
DLC Register (DLCR)
549
Data Register (DTR)
550
Interrupts of CAN Controller
551
Explanation of Operation of CAN Controller
553
Transmission
554
Reception
557
Procedures for Transmitting and Receiving
561
Setting Multiple Message Reception
568
Precautions When Using CAN Controller
570
Program Example of CAN Controller
571
CHAPTER 17 Address Match Detecting Function
573
Overview of Address Match Detection Function
574
Block Diagram of Address Match Detection Function
575
Configuration of Address Match Detection Function
576
Address Detection Control Register (PACSR)
577
Detect Address Setting Registers (PADR0, PADR1)
579
Explanation of Operation of Address Match Detection Function
581
Example of Using Address Match Detection Function
582
Program Example of Address Match Detection Function
587
CHAPTER 18 ROM Mirroring Function Selection Module
589
Overview of ROM Mirroring Function Selection Module
590
ROM Mirroring Function Selection Register (ROMM)
592
Chapter 19 512 Kbit Flash Memory
593
Overview of 512 Kbit Flash Memory
594
Registers and Sector/Bank Configuration of Flash Memory
595
Flash Memory Control Status Register (FMCS)
597
Flash Memory Write Control Register (FWR0/1)
600
How to Start Automatic Algorithm of Flash Memory
605
Reset Vector Addresses in Flash Memory
607
Check the Execution State of Automatic Algorithm
608
Data Polling Flag (DQ7)
610
Toggle Bit Flag (DQ6)
612
Timing Limit over Flag (DQ5)
613
Sector Erase Timer Flag (DQ3)
614
Toggle Bit 2 Flag (DQ2)
615
Details of Programming/Erasing Flash Memory
617
Read/Reset State in Flash Memory
618
Data Programming to Flash Memory
619
Data Erase from Flash Memory (Chip Erase)
621
Erasing any Data in Flash Memory (Sector Erasing)
622
Sector Erase Suspension
624
Sector Erase Resumption
625
Chapter 20 Dual Operation Flash
627
Overview of Dual Operation Flash
628
Register for Dual Operation Flash
629
Operation of Dual Operation Flash
631
Appendix
633
APPENDIX A Instructions
634
Instruction Types
635
Addressing
636
Direct Addressing
638
Indirect Addressing
645
Execution Cycle Count
652
Effective Address Field
654
How to Read the Instruction List
656
F 2 MC-16LX Instruction List
659
Instruction Map
673
APPENDIX B Register Index
695
APPENDIX C Pin Function Index
705
APPENDIX D Interrupt Vector Index
707
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