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MHF2043AT - Mobile 4.32 GB Hard Drive
Fujitsu MHF2043AT - Mobile 4.32 GB Hard Drive Manuals
Manuals and User Guides for Fujitsu MHF2043AT - Mobile 4.32 GB Hard Drive. We have
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Fujitsu MHF2043AT - Mobile 4.32 GB Hard Drive manual available for free PDF download: Product Manual
Fujitsu MHF2043AT - Mobile 4.32 GB Hard Drive Product Manual (225 pages)
Fujitsu Computer Drive User Manual
Brand:
Fujitsu
| Category:
Storage
| Size: 2.29 MB
Table of Contents
Table of Contents
14
Revision History
4
Operating Environment
7
Important Alert Items
10
Manual Organization
12
CHAPTER 1 Device Overview
22
Features
23
Functions and Performance
23
Adaptability
23
Interface
24
Device Specifications
25
Specifications Summary
25
Table 1.1 Specifications (MHE2064AT/MHE2043AT)
25
Table 1.2 Specifications (MHF2043AT/MHF2021AT)
26
Model and Product Number
27
Power Requirements
27
Table 1.4 Model Names and Product Numbers
27
Figure 1.1 Current Fluctuation (Typ.) at +5V When Power Is Turned on
28
Table 1.5 Current and Power Dissipation
28
Environmental Specifications
29
Table 1.6 Environmental Specifications
29
Acoustic Noise
30
Shock and Vibration
30
Table 1.7 Acoustic Noise Specification
30
Table 1.8 Shock and Vibration Specification
30
Reliability
31
Error Rate
32
Media Defects
32
CHAPTER 2 Device Configuration
34
Device Configuration
35
Figure 2.1 Disk Drive Outerview (the MHE Series and MHF Series)
35
Figure 2.2 Configuration of Disk Media Heads
36
System Configuration
37
ATA Interface
37
Drive Connection
37
Drives Connection
37
Figure 2.3 1 Drive System Configuration
37
Figure 2.4 2 Drives Configuration
37
CHAPTER 3 Installation Conditions
40
Dimensions
41
Mounting
43
Figure 3.2 Orientation (Sample: MHE2064AT)
43
Figure 3.3 Mounting Frame Structure
44
Figure 3.4 Surface Temperature Measurement Points (Sample: MHE2064AT)
45
Figure 3.5 Service Area (Sample: MHE2064AT)
46
Cable Connections
47
Device Connector
47
Figure 3.6 Connector Locations (Sample: MHE2064AT)
47
Cable Connector Specifications
48
Device Connection
48
Figure 3.7 Cable Connections
48
Table 3.2 Cable Connector Specifications
48
Power Supply Connector (CN1)
49
Jumper Settings
49
Location of Setting Jumpers
49
Figure 3.8 Power Supply Connector Pins (CN1)
49
Figure 3.9 Jumper Location
49
Factory Default Setting
50
Master Drive-Slave Drive Setting
50
Figure 3.10 Factory Default Setting
50
Figure 3.11 Jumper Setting of Master or Slave Device
50
CSEL Setting
51
Figure 3.12 CSEL Setting
51
Figure 3.13 Example (1) of Cable Select
51
Figure 3.14 Example (2) of Cable Select
52
CHAPTER 4 Theory of Device Operation
54
Outline
55
Subassemblies
55
Disk
55
Head
55
Spindle
56
Actuator
56
Air Filter
56
Figure 4.1 Head Structure
56
Circuit Configuration
57
Figure 4.2 Circuit Configuration
58
Power-On Sequence
59
Self-Calibration
60
Self-Calibration Contents
60
Figure 4.3 Power-On Operation Sequence
60
Execution Timing of Self-Calibration
61
Command Processing During Self-Calibration
62
Read/Write Circuit
62
Read/Write Preamplifier (Preamp)
62
Table 4.1 Self-Calibration Execution Timechart
62
Write Circuit
63
Table 4.2 Write Precompensation Algorithm
63
Figure 4.4 Read/Write Circuit Block Diagram
64
Read Circuit
65
Figure 4.5 Frequency Characteristic of Programmable Filter
65
Digital PLL Circuit
66
Servo Control
67
Servo Control Circuit
67
Figure 4.6 Block Diagram of Servo Control Circuit
67
Figure 4.7 Physical Sector Servo Configuration on Disk Surface
69
Index
70
Data-Surface Servo Format
71
Servo Frame Format
71
Figure 4.8 Servo Frame Format
71
Actuator Motor Control
72
Spindle Motor Control
73
CHAPTER 5 Interface
76
Physical Interface
77
Interface Signals
77
Figure 5.1 Interface Signals
77
Signal Assignment on the Connector
78
Table 5.1 Signal Assignment on the Interface Connector
78
Logical Interface
81
I/O Registers
82
Table 5.2 I/O Registers
82
Command Block Registers
83
Control Block Registers
88
Host Commands
88
Command Code and Parameters
89
Table 5.3 Command Code and Parameters
89
Command Descriptions
91
Figure 5.2 Execution Example of READ MULTIPLE Command
95
Table of Contents
106
Table 5.5 Features Register Values and Settable Modes
114
At Command Issuance (I/O Registers Setting Contents)
117
(Cl) 1F3 H
119
(Dh) DV
119
1F1 (Fr)
119
1F3 (Sn)
119
1F4 (Cl)
119
1F5 (Ch)
119
1F7 (CM)
119
1F7 (ST) Status Information
119
Table 5.6 Diagnostic Code
121
Table 5.7 Features Register Values (Subcommands) and Functions
132
Table 5.8 Format of Device Attribute Value Data
134
Table 5.9 Format of Insurance Failure Threshold Value Data
135
Table 5.10 Contents of Security Password
139
Table 5.11 Contents of SECURITY SET PASSWORD Data
143
Table 5.12 Relationship between Combination of Identifier and Security Level, and Operation of the Lock Function
144
Error Posting
146
Table 5.13 Command Code and Parameters
146
Command Protocol
148
Data Transferring Commands from Device to Host
148
Figure 5.3 Read Sector(S) Command Protocol
149
Data Transferring Commands from Host to Device
150
Figure 5.4 Protocol for Command Abort
150
Figure 5.5 WRITE SECTOR(S) Command Protocol
151
Commands Without Data Transfer
152
DMA Data Transfer Commands
153
Other Commands
153
Figure 5.7 Normal DMA Data Transfer
154
Overview
155
Ultra DMA Feature Set
155
Phases of Operation
156
Ultra DMA Burst Initiation Phase
156
Data Transfer Phase
157
Ultra DMA Burst Termination Phase
157
Initiating an Ultra DMA Data in Burst
158
Ultra DMA Data in Commands
158
Pausing an Ultra DMA Data in Burst
159
The Data in Transfer
159
Terminating an Ultra DMA Data in Burst
160
Initiating an Ultra DMA Data out Burst
163
The Data out Transfer
163
Ultra DMA Data out Commands
163
Pausing an Ultra DMA Data out Burst
164
Terminating an Ultra DMA Data out Burst
165
Ultra DMA CRC Rules
167
Figure 5.8 an Example of Generation of Parallel CRC
168
Table 5.14 Parallel Generation Equation of CRC Polynomial
168
Figure 5.9 Ultra DMA Termination with Pull-Up or Pull-Down
169
Series Termination Required for Ultra DMA
169
Table 5.15 Recommended Series Termination for Ultra DMA
169
PIO Data Transfer
170
Timing
170
Figure 5.10 Data Transfer Timing
171
Figure 5.11 Single Word DMA Data Transfer Timing (Mode 2)
172
Single Word DMA Data Transfer
172
Figure 5.12 Multiword DMA Data Transfer Timing (Mode 2)
173
Multiword DMA Data Transfer
173
Figure 5.13 Starting of Ultra DMA Data in Burst Transfer
174
Starting of Ultra DMA Data in Burst
174
Transfer of Ultra DMA Data
174
Table 5.16 Ultra DMA Data Burst Timing Requirements
175
Ultra DMA Data Burst Timing Requirements
175
Figure 5.14 Sustained Ultra DMA Data in Burst
177
Sustained Ultra DMA Data in Burst
177
Figure 5.15 Host Pausing an Ultra DMA Data in Burst
178
Host Pausing an Ultra DMA Data in Burst
178
Device Terminating an Ultra DMA Data in Burst
179
Figure 5.16 Device Terminating an Ultra DMA Data in Burst
179
Figure 5.17 Host Terminating an Ultra DMA Data in Burst
180
Host Terminating an Ultra DMA Data in Burst
180
Figure 5.18 Initiating an Ultra DMA Data out Burst
181
Initiating an Ultra DMA Data out Burst
181
Figure 5.19 Sustained Ultra DMA Data out Burst
182
Sustained Ultra DMA Data out Burst
182
Device Pausing an Ultra DMA Data out Burst
183
Figure 5.20 Device Pausing an Ultra DMA Data out Burst
183
Figure 5.21 Host Terminating an Ultra DMA Data out Burst
184
Host Terminating an Ultra DMA Data out Burst
184
Device Terminating an Ultra DMA Data in Burst
185
Figure 5.22 Device Terminating an Ultra DMA Data out Burst
185
Figure 5.23 Power on Reset Timing
186
Power-On and Reset
186
Operations
188
CHAPTER 6 Operations
188
Device Response to the Reset
189
Response to Power-On
189
Figure 6.1 Response to Power-On
190
Figure 6.2 Response to Hardware Reset
191
Response to Hardware Reset
191
Figure 6.3 Response to Software Reset
192
Response to Software Reset
192
Figure 6.4 Response to Diagnostic Command
193
Address Translation
194
Response to Diagnostic Command
193
Default Parameters
194
Table 6.1 Default Parameters
194
Figure 6.5 Address Translation (Example in CHS Mode)
195
Power Save
196
Power Save Mode
196
Figure 6.6 Address Translation (Example in LBA Mode)
196
Logical Address
195
Power Commands
198
Defect Management
198
Alternating Defective Sectors
199
Figure 6.7 Sector Slip Processing
199
Spare Area
199
Figure 6.8 Alternate Cylinder Assignment
200
Read-Ahead Cache
201
Caching Operation
201
Data Buffer Configuration
201
Figure 6.9 Data Buffer Configuration
201
Mis-Hit (no Hit)
203
Usage of Read Segment
203
Sequential Read
204
Full Hit (Hit All)
207
Partially Hit
208
Write Cache
209
Glossary
212
Acronyms and Abbreviations
216
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