Fujitsu MHT2080AT - ULTRA ATA 80.0GB Manuals

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Fujitsu MHT2080AT - ULTRA ATA 80.0GB Product Manual

Fujitsu MHT2080AT - ULTRA ATA 80.0GB Product Manual (256 pages)

Fujitsu Computer Drive User Manual

Brand: Fujitsu | Category: Storage | Size: 1.78 MB

Table of Contents

Table of Contents

13
- Revision History
  3
- Operating Environment
  6
- Important Alert Items
  9
- Manual Organization
  11
- CHAPTER 1 Device Overview
  
  21
  - Features
    22
  - Functions and Performance
    22
  - Adaptability
    22
  - Interface
    23
  - Device Specifications
    24
  - Specifications Summary
    24
  - Model and Product Number
    25
  - Power Requirements
    25
  - Environmental Specifications
    28
  - Acoustic Noise
    29
  - Shock and Vibration
    29
  - Reliability
    30
  - Error Rate
    31
  - Media Defects
    31
  - Load/Unload Function
    31
  - Advanced Power Management
    32
- CHAPTER 2 Device Configuration
  
  35
  - Device Configuration
    36
  - System Configuration
    37
  - ATA Interface
    37
  - Drive Connection
    37
  - Drives Connection
    38
- CHAPTER 3 Installation Conditions
  
  39
  - Dimensions
    40
  - Mounting
    41
  - Cable Connections
    47
  - Device Connector
    47
  - Cable Connector Specifications
    48
  - Device Connection
    48
  - Power Supply Connector (CN1)
    49
  - Jumper Settings
    49
  - Location of Setting Jumpers
    49
  - Factory Default Setting
    50
  - Master Drive-Slave Drive Setting
    50
  - CSEL Setting
    51
  - Power up in Standby Setting
    52
- CHAPTER 4 Theory of Device Operation
  
  53
  - Outline
    54
  - Subassemblies
    54
  - Disk
    54
  - Spindle
    54
  - Actuator
    54
  - Air Filter
    55
  - Circuit Configuration
    55
  - Power-On Sequence
    58
  - Self-Calibration
    59
  - Self-Calibration Contents
    59
  - Execution Timing of Self-Calibration
    60
  - Command Processing During Self-Calibration
    61
  - Read/Write Circuit
    61
  - Read/Write Preamplifier (Preamp)
    61
  - Write Circuit
    61
  - Read Circuit
    63
  - Digital PLL Circuit
    64
  - Servo Control
    65
  - Servo Control Circuit
    65
  - Data-Surface Servo Format
    68
  - Servo Frame Format
    70
  - Actuator Motor Control
    71
  - Spindle Motor Control
    72
- CHAPTER 5 Interface
  
  75
  - Physical Interface
    76
  - Interface Signals
    76
  - Signal Assignment on the Connector
    77
  - Logical Interface
    80
  - I/O Registers
    81
  - Command Block Registers
    82
  - Control Block Registers
    87
  - Host Commands
    88
  - Command Code and Parameters
    88
  - Command Descriptions
    92
Table of Contents

157
- 1F7 (CM)
  158
Table of Contents

162
- (DH) X X X DV
  163
- 1F1 (Fr)
  163
- 1F2 (Sc)
  163
- 1F3 (Sn)
  163
- 1F4 (Cl)
  163
- 1F5 (Ch)
  163
- 1F7 (CM)
  163
- At Command Issuance (I-O Register Contents)
  163
- 1F1 (Fr)
  164
- 1F2 (Sc)
  164
- 1F3 (Sn)
  164
- 1F4 (Cl)
  164
- 1F5 (Ch)
  164
- 1F6 (Dh)
  164
- 1F7 (ST) Status Information
  164
  - 1F7 (St)
    164
- At Command Completion (I-O Register Contents)
  164
- (DH) X X X DV
  165
- (ST) Status Information
  165
- 1F1 (ER) Error Information
  165
- 1F2 (Sc)
  165
- 1F3 (Sn)
  165
- 1F4 (Cl)
  165
- 1F5 (Ch)
  165
- 1F6 (Dh) DV
  165
- (DH) X X X DV
  166
- 1F1 (ER) Error Information
  179
- 1F2 (Sc)
  179
- 1F3 (Sn)
  179
- 1F4 (Cl)
  179
- 1F5 (Ch)
  179
- Error Posting
  181
- Command Protocol
  183
- PIO Data Transferring Commands from Device to Host
  183
- PIO Data Transferring Commands from Host to Device
  185
- Commands Without Data Transfer
  187
- DMA Data Transfer Commands
  189
- Other Commands
  189
- Overview
  192
- Ultra DMA Feature Set
  192
- Initiating an Ultra DMA Data in Burst
  193
- Phases of Operation
  193
- Ultra DMA Data in Commands
  193
- Pausing an Ultra DMA Data in Burst
  194
- The Data in Transfer
  194
- Terminating an Ultra DMA Data in Burst
  195
- Initiating an Ultra DMA Data out Burst
  198
- The Data out Transfer
  198
- Ultra DMA Data out Commands
  198
- Pausing an Ultra DMA Data out Burst
  199
- Terminating an Ultra DMA Data out Burst
  200
- Ultra DMA CRC Rules
  202
- Series Termination Required for Ultra DMA
  203
- PIO Data Transfer
  204
- Timing
  204
- Multiword Data Transfer
  205
- Initiating an Ultra DMA Data in Burst
  206
- Ultra DMA Data Transfer
  206
- Ultra DMA Data Burst Timing Requirements
  207
- Sustained Ultra DMA Data in Burst
  210
- Host Pausing an Ultra DMA Data in Burst
  211
- Device Terminating an Ultra DMA Data in Burst
  212
- Host Terminating an Ultra DMA Data in Burst
  213
- Initiating an Ultra DMA Data out Burst
  214
- Sustained Ultra DMA Data out Burst
  215
- Device Pausing an Ultra DMA Data out Burst
  216
- Host Terminating an Ultra DMA Data out Burst
  217
- Device Terminating an Ultra DMA Data out Burst
  218
- Power-On and Reset
  219
- CHAPTER 6 Operations
  
  221
  - Device Response to the Reset
    222
  - Response to Power-On
    222
  - Response to Hardware Reset
    223
  - Response to Software Reset
    225
  - Response to Diagnostic Command
    226
    
    Power Save
    227
    
    Defect Processing
    229
    
    Using the Read Segment Buffer
    235
    
    Write Cache
    239
    
    Acronyms and Abbreviations
    247

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