Hitachi SH7751R Manuals

Manuals and User Guides for Hitachi SH7751R. We have 1 Hitachi SH7751R manual available for free PDF download: Hardware Manual

Hitachi SH7751R Hardware Manual (1104 pages)

SuperH RISC engine

Brand: Hitachi | Category: Engine | Size: 5.43 MB

Table of Contents
6
Section 1 Overview

40
- SH7751 Series Features
  40
Tables

41
- Figure 13.61 MPX Interface Timing
  41
- Table 1.1 SH7751 Series Features
  41
- Block Diagram
  49
- Figure 1.1 Block Diagram of SH7751 Series Functions
  49
- Figures
  
  49
- Figure 1.2 Pin Arrangement (256-Pin QFP)
  50
- Pin Arrangement
  50
- Figure 1.3 Pin Arrangement (256-Pin BGA)
  51
- Pin Functions
  52
  - Pin Functions (256-Pin QFP)
    52
  - Table 1.2 Pin Functions
    52
  - Pin Functions (256-Pin BGA)
    63
  - Table 1.3 Pin Functions
    63
Section 2 Programming Model

74
- Data Formats
  74
- Figure 2.1 Data Formats
  74
- Register Configuration
  75
- Memory-Mapped Registers
  85
- Data Format in Registers
  86
- Data Formats in Memory
  86
- Figure 2.5 Data Formats in Memory
  86
- Processor States
  87
- Processor Modes
  88
- Figure 2.6 Processor State Transitions
  88
Memory Management Unit (MMU)

90
- Overview
  90
  - Features
    90
  - Role of the MMU
    90
  - Figure 3.1 Role of the MMU
    92
  - Register Configuration
    93
  - Caution
    93
  - Table 3.1 MMU Registers
    93
- Register Descriptions
  94
- Figure 3.2 MMU-Related Registers
  94
- Address Space
  97
  - Physical Address Space
    97
  - Figure 3.3 Physical Address Space (MMUCR.AT = 0)
    98
  - Figure 3.4 P4 Area
    99
  - External Memory Space
    100
  - Figure 3.5 External Memory Space
    100
  - Virtual Address Space
    101
  - Figure 3.6 Virtual Address Space (MMUCR.AT = 1)
    101
  - On-Chip RAM Space
    102
  - Address Translation
    102
  - Single Virtual Memory Mode and Multiple Virtual Memory Mode
    103
  - Address Space Identifier (ASID)
    103
- TLB Functions
  104
- MMU Functions
  111
  - MMU Hardware Management
    111
  - MMU Software Management
    111
  - MMU Instruction (LDTLB)
    111
  - Hardware ITLB Miss Handling
    112
  - Figure 3.12 Operation of LDTLB Instruction
    112
  - Avoiding Synonym Problems
    113
- MMU Exceptions
  114
- Memory-Mapped TLB Configuration
  119
  - ITLB Address Array
    120
  - Figure 3.13 Memory-Mapped ITLB Address Array
    120
  - ITLB Data Array 1
    121
  - Figure 3.14 Memory-Mapped ITLB Data Array 1
    121
  - ITLB Data Array 2
    122
  - UTLB Address Array
    122
  - Figure 3.15 Memory-Mapped ITLB Data Array 2
    122
  - Figure 3.16 Memory-Mapped UTLB Address Array
    123
  - UTLB Data Array 1
    124
  - Figure 3.17 Memory-Mapped UTLB Data Array 1
    124
  - UTLB Data Array 2
    125
  - Figure 3.18 Memory-Mapped UTLB Data Array 2
    125
Section 4 Caches

126
- Overview
  126
  - Features
    126
  - Table 4.1 Cache Features (SH7751)
    126
  - Register Configuration
    127
  - Table 4.2 Cache Features (SH7751R)
    127
  - Table 4.3 Store Queue Features
    127
  - Table 4.4 Cache Control Registers
    127
- Register Descriptions
  128
- Figure 4.1 Cache and Store Queue Control Registers (CCR)
  128
- Operand Cache (OC)
  130
  - Configuration
    130
  - Figure 4.2 Configuration of Operand Cache (SH7751)
    131
  - Figure 4.3 Configuration of Operand Cache (SH7751R)
    132
  - Read Operation
    133
  - Write Operation
    134
  - Write-Back Buffer
    136
  - Write-Through Buffer
    136
  - RAM Mode
    136
  - Figure 4.4 Configuration of Write-Back Buffer
    136
  - Figure 4.5 Configuration of Write-Through Buffer
    136
  - OC Index Mode
    138
  - Coherency between Cache and External Memory
    138
  - Prefetch Operation
    138
- Instruction Cache (IC)
  138
  - Configuration
    138
  - Figure 4.6 Configuration of Instruction Cache (SH7751)
    139
  - Figure 4.7 Configuration of Instruction Cache (SH7751R)
    140
  - Read Operation
    141
  - IC Index Mode
    141
- Memory-Mapped Cache Configuration (SH7751)
  142
  - IC Address Array
    142
  - IC Data Array
    143
  - Figure 4.8 Memory-Mapped IC Address Array
    143
  - OC Address Array
    144
  - Figure 4.9 Memory-Mapped IC Data Array
    144
  - OC Data Array
    145
  - Figure 4.10 Memory-Mapped OC Address Array
    145
- Memory-Mapped Cache Configuration (SH7751R)
  146
  - Figure 4.11 Memory-Mapped OC Data Array
    146
  - IC Address Array
    147
  - Figure 4.12 Memory-Mapped IC Address Array
    148
  - IC Data Array
    148
  - Figure 4.13 Memory-Mapped IC Data Array
    149
  - OC Address Array
    149
  - Figure 4.14 Memory-Mapped OC Address Array
    150
  - OC Data Array
    150
  - Figure 4.15 Memory-Mapped OC Data Array
    151
  - Summary of Memory-Mapped OC Addresses
    151
- Store Queues
  152
  - SQ Configuration
    152
  - SQ Writes
    152
  - Transfer to External Memory
    152
  - Figure 4.16 Store Queue Configuration
    152
  - Determination of SQ Access Exception
    154
  - SQ Read (SH7751R Only)
    154
  - SQ Usage Notes
    155
Section 5 Exceptions

158
- Overview
  158
  - Features
    158
  - Register Configuration
    158
  - Table 5.1 Exception-Related Registers
    158
- Register Descriptions
  159
- Figure 5.1 Register Bit Configurations
  159
- Exception Handling Functions
  160
  - Exception Handling Flow
    160
  - Exception Handling Vector Addresses
    160
- Exception Types and Priorities
  161
- Table 5.2 Exceptions
  161
- Exception Flow
  164
- Description of Exceptions
  167
  - Resets
    168
  - Table 5.3 Types of Reset
    169
  - General Exceptions
    173
  - Interrupts
    187
  - Priority Order with Multiple Exceptions
    190
- Usage Notes
  191
- Restrictions
  192
Section 6 Floating-Point Unit

194
- Overview
  194
- Data Formats
  194
- Registers
  198
- Rounding
  201
- Floating-Point Exceptions
  202
- Graphics Support Functions
  203
  - Geometric Operation Instructions
    203
  - Pair Single-Precision Data Transfer
    205
Section 7 Instruction Set

206
Section 8 Pipelining

226
- Pipelines
  226
- Figure 8.1 Basic Pipelines
  227
- Figure 8.2 Instruction Execution Patterns
  228
- Parallel-Executability
  233
- Table 8.1 Instruction Groups
  233
- Execution Cycles and Pipeline Stalling
  237
- Table 8.2 Parallel-Executability
  237
- Figure 8.3 Examples of Pipelined Execution
  240
- Table 8.3 Execution Cycles
  244
Section 9 Power-Down Modes

254
Section 10 Clock Oscillation Circuits

280
- Overview
  280
  - Features
    280
- Overview of CPG
  282
  - Block Diagram of CPG
    282
  - Figure 10.1(1) Block Diagram of CPG (SH7751)
    282
  - Figure 10.1(2) Block Diagram of CPG (SH7751R)
    283
  - CPG Pin Configuration
    285
  - CPG Register Configuration
    285
  - Table 10.1 CPG Pins
    285
  - Table 10.2 CPG Register
    285
- Clock Operating Modes
  286
- Table 10.3(1) Clock Operating Modes (SH7751)
  286
- Table 10.3(2) Clock Operating Modes (SH7751R)
  286
- Table 10.4 FRQCR Settings and Internal Clock Frequencies
  287
- CPG Register Description
  288
  - Frequency Control Register (FRQCR)
    288
- Changing the Frequency
  290
- Output Clock Control
  292
- Overview of Watchdog Timer
  292
  - Block Diagram
    292
  - Figure 10.2 Block Diagram of WDT
    292
  - Register Configuration
    293
- WDT Register Descriptions
  293
- Using the WDT
  297
  - Standby Clearing Procedure
    297
  - Frequency Changing Procedure
    297
  - Using Watchdog Timer Mode
    298
  - Using Interval Timer Mode
    298
- Notes on Board Design
  299
- Figure 10.4 Points for Attention When Using Crystal Resonator
  299
- Figure 10.5 Points for Attention When Using PLL Oscillator Circuit
  300
Section 11 Realtime Clock (RTC)

302
- Overview
  302
  - Features
    302
  - Block Diagram
    303
  - Figure 11.1 Block Diagram of RTC
    303
  - Pin Configuration
    304
  - Register Configuration
    304
  - Table 11.1 RTC Pins
    304
  - Table 11.2 RTC Registers
    304
- Register Descriptions
  306
  - 64 Hz Counter (R64CNT)
    306
  - Second Counter (RSECCNT)
    306
  - Minute Counter (RMINCNT)
    307
  - Hour Counter (RHRCNT)
    307
  - Day-Of-Week Counter (RWKCNT)
    308
  - Day Counter (RDAYCNT)
    309
  - Month Counter (RMONCNT)
    309
  - Year Counter (RYRCNT)
    310
  - Second Alarm Register (RSECAR)
    311
  - Minute Alarm Register (RMINAR)
    311
  - Hour Alarm Register (RHRAR)
    312
  - Day-Of-Week Alarm Register (RWKAR)
    312
  - Day Alarm Register (RDAYAR)
    313
  - Month Alarm Register (RMONAR)
    314
  - RTC Control Register 1 (RCR1)
    314
  - RTC Control Register 2 (RCR2)
    316
  - RTC Control Register (RCR3) and Year-Alarm Register (RYRAR)
    319
  - (SH7751R Only)
    319
- Operation
  320
- Interrupts
  324
- Usage Notes
  324
Section 12 Timer Unit (TMU)

326
- Overview
  326
  - Features
    326
  - Block Diagram
    327
  - Pin Configuration
    327
  - Figure 12.1 Block Diagram of TMU
    327
  - Table 12.1 TMU Pins
    327
  - Register Configuration
    328
  - Table 12.2 TMU Registers
    328
- Register Descriptions
  329
  - Timer Output Control Register (TOCR)
    329
  - Timer Start Register (TSTR)
    330
  - Timer Start Register 2 (TSTR2)
    331
  - Timer Constant Registers (TCOR)
    332
  - Timer Counters (TCNT)
    332
  - Timer Control Registers (TCR)
    333
  - Input Capture Register (TCPR2)
    336
- Operation
  337
- Interrupts
  341
- Figure 12.7 Operation Timing When Using Input Capture Function
  341
- Usage Notes
  342
  - Register Writes
    342
  - TCNT Register Reads
    342
  - Resetting the RTC Frequency Divider
    342
  - External Clock Frequency
    342
  - Table 12.3 TMU Interrupt Sources
    342
Section 13 Bus State Controller (BSC)

344
Section 14 Direct Memory Access Controller (DMAC)

502
Section 15 Serial Communication Interface (SCI)

608
Section 16 Serial Communication Interface with FIFO (SCIF)

672
Section 17 Smart Card Interface

718
Section 18 I/O Ports

746
- Overview
  746
  - Features
    746
  - Block Diagrams
    747
  - Figure 18.1 16-Bit Port a
    747
  - Figure 18.2 16-Bit Port B
    748
  - Figure 18.3 SCK Pin
    749
  - Figure 18.4 Txd Pin
    750
  - Figure 18.5 Rxd Pin
    750
  - Figure 18.6 Md1/Txd2 Pin
    751
  - Figure 18.7 Md2/Rxd2 Pin
    751
  - Figure 18.8 MD0/SCK2 Pin
    752
  - Figure 18.9 MD7/CTS2 Pin
    753
  - Pin Configuration
    754
  - Figure 18.10 MD8/RTS2 Pin
    754
  - Table 18.1 32-Bit General-Purpose I/O Port Pins
    754
  - Table 18.2 SCI I/O Port Pins
    756
  - Table 18.3 SCIF I/O Port Pins
    756
  - Register Configuration
    757
  - Table 18.4 I/O Port Registers
    757
- Register Descriptions
  758
  - Port Control Register a (PCTRA)
    758
  - Port Data Register a (PDTRA)
    759
  - Port Control Register B (PCTRB)
    759
  - Port Data Register B (PDTRB)
    761
  - GPIO Interrupt Control Register (GPIOIC)
    761
  - Serial Port Register (SCSPTR1)
    762
  - Serial Port Register (SCSPTR2)
    764
Section 19 Interrupt Controller (INTC)

768
- Overview
  768
  - Features
    768
  - Block Diagram
    768
  - Figure 19.1 Block Diagram of INTC
    769
  - Pin Configuration
    770
  - Register Configuration
    770
  - Table 19.1 INTC Pins
    770
  - Table 19.2 INTC Registers
    770
- Interrupt Sources
  771
- Register Descriptions
  778
- INTC Operation
  786
  - Interrupt Operation Sequence
    786
  - Figure 19.3 Interrupt Operation Flowchart
    787
  - Multiple Interrupts
    788
  - Interrupt Masking with MAI Bit
    788
- Interrupt Response Time
  789
- Table 19.8 Interrupt Response Time
  789
Section 20 User Break Controller (UBC)

790
- Overview
  790
  - Features
    790
  - Block Diagram
    791
  - Figure 20.1 Block Diagram of User Break Controller
    791
  - Table 20.1 UBC Registers
    792
- Register Descriptions
  793
  - Access to UBC Registers
    793
  - Break Address Register a (BARA)
    794
  - Break ASID Register a (BASRA)
    795
  - Break Address Mask Register a (BAMRA)
    795
  - Break Bus Cycle Register a (BBRA)
    796
  - Break Address Register B (BARB)
    798
  - Break ASID Register B (BASRB)
    798
  - Break Address Mask Register B (BAMRB)
    798
  - Break Data Register B (BDRB)
    798
  - Break Data Mask Register B (BDMRB)
    799
  - Break Bus Cycle Register B (BBRB)
    800
  - Break Control Register (BRCR)
    800
- Operation
  802
- User Break Debug Support Function
  810
- Figure 20.2 User Break Debug Support Function Flowchart
  811
- Examples of Use
  812
- User Break Controller Stop Function
  814
Section 21 Hitachi User Debug Interface (H-UDI)

816
- Overview
  816
  - Features
    816
  - Block Diagram
    816
  - Figure 21.1 Block Diagram of H-UDI Circuit
    817
  - Pin Configuration
    818
  - Table 21.1 H-UDI Pins
    818
  - Register Configuration
    819
  - Table 21.2 H-UDI Registers
    819
- Register Descriptions
  820
  - Instruction Register (SDIR)
    820
  - Data Register (SDDR)
    821
  - Bypass Register (SDBPR)
    821
  - Interrupt Factor Register (SDINT)
    822
  - Boundary Scan Register (SDBSR)
    822
  - Table 21.3 Structure of Boundary Scan Register
    823
- Operation
  837
  - TAP Control
    837
  - Figure 21.2 TAP Control State Transition Diagram
    837
  - H-UDI Reset
    838
  - H-UDI Interrupt
    838
  - Figure 21.3 H-UDI Reset
    838
  - Boundary Scan (EXTEST, SAMPLE/PRELOAD, BYPASS)
    839
- Usage Notes
  839
Section 22 PCI Controller (PCIC)

840
Section 23 Electrical Characteristics

968
Appendix A Address List

1070
- Table A.1 Address List
  1070
Appendix B Package Dimensions

1078
- Figure B.1 Package Dimensions (256-Pin QFP)
  1078
- Figure B.2 Package Dimensions (256-Pin BGA)
  1079
Appendix C Mode Pin Settings

1080
- Table C.1 Clock Operating Modes (SH7751)
  1080
- Table C.2 Clock Operating Modes (SH7751R)
  1080
- Table C.3 Area 0 Memory Map and Bus Width
  1081
- Table C.4 Endian
  1081
- Table C.5 Master/Slave
  1081
- Table C.6 Clock Input
  1081
- Table C.7 PCI Mode
  1082
Appendix D Pin Functions

1083
Appendix E Synchronous DRAM Address Multiplexing Tables

1089
Appendix F Instruction Prefetching and Its Side Effects

1100
- Figure F.1 Instruction Prefetch
  1100
Appendix G Power-On and Power-Off Procedures

1101
- Figure G.1 Power-On and Power-Off Procedures
  1101
Appendix H List of Models

1102
- Table H.1 SH7751 Series Models
  1102

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Hitachi SH7751R Manuals

Hitachi SH7751R Hardware Manual (1104 pages)

Table of Contents

Section 1 Overview

Tables

Figures

Section 2 Programming Model

Memory Management Unit (MMU)

Section 4 Caches

Section 5 Exceptions

Section 6 Floating-Point Unit

Section 7 Instruction Set

Section 8 Pipelining

Section 9 Power-Down Modes

Section 10 Clock Oscillation Circuits

Section 11 Realtime Clock (RTC)

Section 12 Timer Unit (TMU)

Section 13 Bus State Controller (BSC)

Section 14 Direct Memory Access Controller (DMAC)

Section 15 Serial Communication Interface (SCI)

Section 16 Serial Communication Interface with FIFO (SCIF)

Section 17 Smart Card Interface

Section 18 I/O Ports

Section 19 Interrupt Controller (INTC)

Section 20 User Break Controller (UBC)

Section 21 Hitachi User Debug Interface (H-UDI)

Section 22 PCI Controller (PCIC)

Section 23 Electrical Characteristics

Appendix A Address List

Appendix B Package Dimensions

Appendix C Mode Pin Settings

Appendix D Pin Functions

Appendix E Synchronous DRAM Address Multiplexing Tables

Appendix F Instruction Prefetching and Its Side Effects

Appendix G Power-On and Power-Off Procedures

Appendix H List of Models

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