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Motorola DSP56012 manual available for free PDF download: User Manual
Motorola DSP56012 User Manual (270 pages)
24-Bit Digital Signal Processor
Brand:
Motorola
| Category:
Signal Processors
| Size: 2.31 MB
Table of Contents
Table of Contents
3
List of Figures
13
Introduction
23
Manual Organization
24
Manual Conventions
25
Table 1-1 High True / Low True Signal Conventions
26
Dsp56012 Features
26
Table 1-2 DSP56012 Internal Memory Configurations
27
Dsp56012 Architectural Overview
28
Figure 1-1 DSP56012 Block Diagram
29
DSP Core Processor
30
Data Arithmetic and Logic Unit (Data ALU)
31
Address Generation Unit (AGU)
31
Program Control Unit
32
Data Buses
32
Address Buses
32
Phase Lock Loop (PLL)
32
On-Chip Emulation (Once) Port
33
Peripheral Modules
30
Memories
33
Program Memory
33
Table 1-3 Interrupt Starting Addresses and Sources
33
Data Memory
35
Y Data Memory
35
On-Chip Memory Configuration Bits
35
Table 1-4 Internal Memory Configurations
35
Memory Configuration Bits
36
External Memory
36
Bootstrap ROM
36
Reserved Memory Spaces
36
Input/Output
36
Table 1-5 On-Chip Peripheral Memory Map
37
Parallel Host Interface (HI)
38
Serial Host Interface (SHI)
38
Digital Audio Transmitter (DAX)
39
General Purpose I/O
39
Serial Audio Interface (SAI)
39
Table 2-1 DSP56012 Functional Signal Groupings
43
Signal Groupings
43
Figure 2-1 DSP56012 Signals
44
Table 2-2 Power Inputs
45
Power
45
Table 2-3 Grounds
46
Ground
46
Table 2-4 Phase Lock Loop Signals
47
Phase Lock Loop (Pll)
47
Interrupt and Mode Control
48
Table 2-5 Interrupt and Mode Control
48
Host Interface (Hi)
50
Table 2-6 Host Interface
50
Serial Host Interface (Shi)
53
Table 2-7 Serial Host Interface (SHI) Signals
53
Serial Audio Interface (Sai)
56
SAI Receive Section
56
Table 2-8 Serial Audio Interface (SAI) Receive Signals
56
SAI Transmit Section
57
Table 2-9 Serial Audio Interface (SAI) Transmit Signals
57
General Purpose Input/Output (Gpio)
58
Digital Audio Interface (Dax)
58
Table 2-10 General Purpose I/O (GPIO) Signals
58
Table 2-11 Digital Audio Interface (DAX) Signals
58
Once Port
59
Table 2-12 On-Chip Emulation Port (Once) Signals
59
Dsp56012 Data and Program Memory
63
Introduction
63
Memory, Operating Modes, and Interrupts
63
Table 3-1 Internal Memory Configurations
63
And y Data ROM
64
Bootstrap ROM
64
Dsp56012 Data and Program Memory Maps
64
Reserved Memory Spaces
65
Dynamic Switch of Memory Configurations
68
Internal I/O Memory Map
70
Table 3-2 Internal I/O Memory Map
70
Operating Mode Register (Omr)
72
DSP Operating Mode (MC, MB, MA)-Bits 4, 1, and 0
72
Program RAM Enable a and Program RAM Enable B
72
Program RAM Enable a and Program RAM Enable B (PEA and PEB)-Bits 2 and
72
Stop Delay (SD)-Bit 6
72
Figure 3-5 Operating Mode Register (OMR)
72
Program RAM Enable a (PEA)-Bit 2
72
Program RAM Enable B (PEB)-Bit 3
72
Operating Modes
73
Table 3-3 Operating Modes
73
Interrupt Priority Register
75
Figure 3-6 Interrupt Priority Register (Addr X:$FFFF)
76
Table 3-4 Interrupt Priorities
76
Table 3-5 Interrupt Vectors
77
Phase Lock Loop (Pll) Configuration
79
Figure 3-7 PLL Configuration
80
Operation on Hardware Reset
80
Figure 4-1 Port B Interface
83
Introduction
83
Port B Configuration
83
Figure 4-2 Parallel Port B Registers
84
Figure 4-3 Port B GPIO Signals and Registers
85
Figure 4-4 Port B I/O Pin Control Logic
86
Port B Control (PBC) Register
86
Port B Data (PBD) Register
87
Port B Data Direction Register (PBDDR)
87
Figure 4-5 Instructions to Write/Read Parallel Data with Port B
88
Programming the Gpio
88
Host Interface (Hi)
89
Figure 4-6 I/O Port B Configuration
89
HI Features
90
HI Block Diagram
91
Figure 4-7 HI Block Diagram
92
HI-DSP Viewpoint
92
Programming Model-DSP Viewpoint
93
Figure 4-8 HI Programming Model-DSP Viewpoint
94
HI Control Register (HCR)
94
HCR HI Receive Interrupt Enable (HRIE)-Bit 0
95
HCR HI Command Interrupt Enable (HCIE)-Bit 2
95
HCR HI Flag 2 (HF2)-Bit 3
95
HCR HI Flag 3 (HF3)-Bit 4
95
HCR HI Transmit Interrupt Enable (HTIE)-Bit 1
95
HCR Reserved-Bits 5, 6, and 7
96
HI Status Register (HSR)
96
HSR HI Receive Data Full (HRDF)-Bit 0
96
HSR HI Transmit Data Empty (HTDE)-Bit 1
96
HSR HI Command Pending (HCP)-Bit 2
97
HSR HI Flag 1 (HF1)-Bit 4
97
HSR Reserved-Bits 5 and 6
98
HSR DMA Status (DMA)-Bit 7
98
Figure 4-9 HI Flag Operation
98
HI Receive Data Register (HORX)
98
HI Transmit Data Register (HOTX)
99
Register Contents after Reset
99
Table 4-1 HI Registers after Reset-DSP CPU Side
99
DSP Interrupts
100
HI Usage Considerations-DSP Side
101
HI-Host Processor Viewpoint
101
Programming Model-Host Processor Viewpoint
101
Host Command
102
Figure 4-10 Host Processor Programming Model-Host Side
103
Interrupt Control Register (ICR)
104
ICR Receive Request Enable (RREQ)-Bit 0
104
ICR Transmit Request Enable (TREQ)-Bit 1
104
Figure 4-11 HI Register Map
104
ICR Reserved-Bit 2
105
ICR HI Flag 0 (HF0)-Bit 3
105
Table 4-2 HOREQ Pin Definition
105
ICR HI Flag 1 (HF1)-Bit 4
106
ICR HI Mode Control (HM1 and HM0)-Bits 5 and 6
106
Figure 4-12 HSR and HCR Operation
106
Table 4-3 HI Mode Bit Definition
106
ICR Initialize Bit (INIT)-Bit 7
107
HI Initialization
107
Table 4-4 HOREQ Pin Definition
108
Command Vector Register (CVR)
109
CVR HI Vector (HV)-Bits 0-5
109
Figure 4-13 Command Vector Register
109
CVR Reserved-Bit 6
110
CVR Host Command (HC)-Bit 7
110
Interrupt Status Register (ISR)
110
ISR Receive Data Register Full (RXDF)-Bit 0
110
ISR Transmit Data Register Empty (TXDE)-Bit 1
111
ISR Transmitter Ready (TRDY)-Bit 2
111
ISR HI Flag 2 (HF2)-Bit 3 (Read Only)
111
ISR HI Flag 3 (HF3)-Bit 4 (Read Only)
111
ISR Reserved-Bit 5
111
ISR Host Request (HOREQ)-Bit 7
112
Interrupt Vector Register (IVR)
112
Receive Byte Registers (RXH, RXM, RXL)
112
Transmit Byte Registers (TXH, TXM, TXL)
113
Registers after Reset
113
Table 4-5 HI Registers after Reset (Host Side)
114
HI Signals
115
HI Data Bus (H0-H7)
115
HI Address (HOA2-HOA0)
115
HI Read/Write (HR/W)
115
HI Enable (HEN)
115
Host Request (HOREQ)
115
Host Acknowledge (HACK)
116
Table 4-6 Port B Pin Definitions
116
Servicing the HI
117
HI-Host Processor Data Transfer
117
Figure 4-14 Host Processor Transfer Timing
117
Host Interrupts Using Host Request (HOREQ)
118
Polling
118
Servicing Non-DMA Interrupts
119
Figure 4-15 Interrupt Vector Register Read Timing
120
Figure 4-16 HI Interrupt Structure
120
Servicing DMA Interrupts
121
Figure 4-17 DMA Transfer Logic and Timing
121
Host Interface Application Examples
122
HI Initialization
122
Figure 4-18 HI Initialization Flowchart
122
Figure 4-19 HI Initialization-DSP Side
123
Figure 4-20 HI Initialization-Host Side, Interrupt Mode
124
Polling/Interrupt Controlled Data Transfer
125
Figure 4-21 HI Mode and INIT Bits
125
Figure 4-22 HI Initialization-Host Side, Polling Mode
126
Figure 4-23 HI Configuration-Host Side
126
Figure 4-24 HI Initialization-Host Side, DMA Mode
127
Host to DSP-Data Transfer
129
Host to DSP-Command Vector
131
Figure 4-28 Receive Data from Host-Main Program
133
Figure 4-29 Receive Data from Host Interrupt Routine
133
Figure 4-30 Transmit/Receive Byte Registers
134
Host to DSP-Bootstrap Loading Using the HI
134
Figure 4-31 Bootstrap Using the Host Interface
135
DSP to Host-Data Transfer
136
DMA Data Transfer
139
Figure 4-34 Main Program: Transmit 24-Bit Data to Host
139
Figure 4-35 HI Hardware-DMA Mode
140
Figure 4-36 DMA Transfer and HI Interrupts
141
Host to DSP-Internal Processing
141
Host to DSP-DMA Procedure
142
DSP to HI -Internal Processing
144
DSP to Host-DMA Procedure
145
HI Port Usage Considerations-Host Side
145
Overwriting Transmit Byte Registers
146
Synchronization of Status Bits from DSP to Host
146
Cancelling a Pending Host Command Interrupt
146
Overwriting the Host Vector
146
Coordinating Data Transfers
147
Unused Pins
147
Introduction
151
Figure 5-1 Serial Host Interface Block Diagram
152
Serial Host Interface Internal Architecture
152
Shi Clock Generator
153
Serial Host Interface Programming Model
153
Figure 5-2 SHI Clock Generator
153
Figure 5-3 SHI Programming Model-Host Side
153
Table 5-1 SHI Interrupt Vectors
155
Table 5-2 SHI Internal Interrupt Priorities
155
Figure 5-5 SHI I/O Shift Register (IOSR)
156
SHI Host Transmit Data Register (HTX)-DSP Side
156
SHI Input/Output Shift Register (IOSR)-Host Side
156
SHI Clock Control Register (HCKR)-DSP Side
157
Serial Host Interface Programming Model
157
Clock Phase and Polarity (CPHA and CPOL)-Bits
158
Figure 5-6 SPI Data-To-Clock Timing Diagram
158
HCKR Prescaler Rate Select (HRS)-Bit 2
159
HCKR Divider Modulus Select (HDM[5:0])-Bits 8-3
160
HCKR Filter Mode (HFM[1:0]) - Bits 13-12
160
HCKR Reserved Bits-Bits 23-14, 11-9
160
Table 5-3 SHI Noise Reduction Filter Mode
160
SHI Host Receive Data FIFO (HRX)-DSP Side
157
SHI Slave Address Register (HSAR)-DSP Side
157
HSAR Reserved Bits-Bits 17-0,19
157
SHI Control/Status Register (HCSR)-DSP Side
161
HCSR Host Enable (HEN)-Bit 0
161
SHI Individual Reset
161
Hcsr I
161
HCSR Serial Host Interface Mode (HM[1:0])-Bits
162
HCSR Reserved Bits-Bits 23, 18, 16, and 4
162
HCSR FIFO-Enable Control (HFIFO)-Bit 5
162
HCSR Master Mode (HMST)-Bit 6
162
Table 5-4 SHI Data Size
162
HCSR Host-Request Enable (HRQE[1:0])-Bits 8-7
163
HCSR Idle (HIDLE)-Bit 9
163
Table 5-5 HREQ Function in SHI Slave Modes
163
HCSR Bus-Error Interrupt Enable (HBIE)-Bit 10
164
HCSR Transmit-Interrupt Enable (HTIE)-Bit 11
164
HCSR Receive Interrupt Enable (HRIE[1:0])-Bits
164
HCSR Host Transmit Underrun Error (HTUE)-Bit 14
165
HCSR Host Transmit Data Empty (HTDE)-Bit 15
165
Table 5-6 HCSR Receive Interrupt Enable Bits
165
Host Receive Overrun Error (HROE)-Bit 20
166
Host Bus Error (HBER)-Bit 21
166
HCSR Host Busy (Hbusy)—Bit 22
167
Characteristics of the Spi Bus
167
Characteristics of the I
168
Overview
168
Characteristics of the I2C Bus
168
Figure 5-8 I 2 C Start and Stop Events
169
Figure 5-9 Acknowledgment on the I
169
C Data Transfer Formats
170
Figure 5-10 I
170
Figure 5-11 I
170
Shi Programming Considerations
171
SPI Slave Mode
171
SPI Master Mode
172
I 2 C Slave Mode
173
Receive Data in I 2 C Slave Mode
174
Transmit Data in I 2 C Slave Mode
175
C Master Mode
175
Receive Data in I C Master Mode
177
Transmit Data in I C Master Mode
177
SHI Operation During Stop
178
Introduction
181
Serial Audio Interface Internal Architecture
182
Baud-Rate Generator
182
Figure 6-1 SAI Baud-Rate Generator Block Diagram
182
Receive Section Overview
183
Figure 6-2 SAI Receive Section Block Diagram
183
SAI Transmit Section Overview
184
Figure 6-3 SAI Transmit Section Block Diagram
185
Serial Audio Interface Programming Model
186
Figure 6-4 SAI Registers
186
Baud Rate Control Register (BRC)
187
Table 6-1 SAI Interrupt Vector Locations
187
Table 6-2 SAI Internal Interrupt Priorities
187
BRC Reserved Bits-Bits 15-9
188
Prescale Modulus Select (PM[7:0])-Bits 7-0
188
Prescaler Range (PSR)-Bit 8
188
Receiver Control/Status Register (RCS)
188
RCS Receiver 0 Enable (R0EN)-Bit 0
188
RCS Receiver 1 Enable (R1EN)-Bit 1
189
RCS Reserved Bit-Bits 13 and 2
189
RCS Receiver Word Length Control (RWL[1:0])-Bits 4 and 5
189
Table 6-3 Receiver Word Length Control
189
RCS Receiver Data Shift Direction (RDIR)-Bit 6
190
RCS Receiver Left Right Selection (RLRS)-Bit 7
190
Figure 6-5 Receiver Data Shift Direction (RDIR) Programming
190
Figure 6-6 Receiver Left/Right Selection (RLRS) Programming
190
RCS Receiver Clock Polarity (RCKP)-Bit 8
191
RCS Receiver Relative Timing (RREL)-Bit 9
191
Figure 6-7 Receiver Clock Polarity (RCKP) Programming
191
RCS Receiver Data Word Truncation (RDWT)-Bit 10
192
Figure 6-8 Receiver Relative Timing (RREL) Programming
192
Figure 6-9 Receiver Data Word Truncation (RDWT) Programming
192
RCS Receiver Interrupt Enable (RXIE)-Bit 11
193
RCS Receiver Interrupt Location (RXIL)-Bit 12
193
RCS Receiver Left Data Full (RLDF)-Bit 14
194
RCS Receiver Right Data Full (RRDF)-Bit 15
194
SAI Receive Data Registers (RX0 and RX1)
195
Transmitter Control/Status Register (TCS)
195
TCS Transmitter 0 Enable (T0EN)-Bit 0
195
TCS Transmitter 1 Enable (T1EN)-Bit 1
195
TCS Transmitter Master (TMST)-Bit 3
196
TCS Transmitter Word Length Control (TWL[1:0])-Bits 4 & 5
196
TCS Transmitter Data Shift Direction (TDIR)-Bit 6
196
Table 6-4 Transmitter Word Length
196
TCS Transmitter Left Right Selection (TLRS)-Bit 7
197
Figure 6-10 Transmitter Data Shift Direction (TDIR) Programming
197
Figure 6-11 Transmitter Left/Right Selection (TLRS) Programming
197
TCS Transmitter Relative Timing (TREL)-Bit 9
198
TCS Transmitter Data Word Expansion (TDWE)-Bit 10
198
Figure 6-12 Transmitter Clock Polarity (TCKP) Programming
198
Figure 6-13 Transmitter Relative Timing (TREL) Programming
198
Figure 6-14 Transmitter Data Word Expansion (TDWE) Programming
199
TCS Transmitter Interrupt Enable (Txie)—Bit 11
199
TCS Transmitter Interrupt Location (TXIL)-Bit 12
200
TCS Reserved Bit—Bit 13
200
TCS Transmitter Left Data Empty (TLDE)-Bit 14
200
TCS Transmitter Right Data Empty (TRDE)-Bit 15
201
SAI Transmit Data Registers (TX2, TX1 and TX0)
201
Programming Considerations
202
SAI Operation During Stop
202
Initiating a Transmit Session
202
Using a Single Interrupt to Service both Receiver and
202
SAI State Machine
203
Introduction
207
Gpio Programming Model
207
Figure 7-1 GPIO Control/Data Register
207
GPIOR Control Bits (GC[7:0])-Bits 23-16
208
GPIOR Data Bits (GD[7:0])-Bits 7-0
208
GPIOR Data Direction Bits (GDD[7:0])-Bits 15-8
208
Table 7-1 GPIO Pin Configuration
208
Figure 7-2 GPIO Circuit Diagram
209
Overview
213
Figure 8-1 Digital Audio Transmitter (DAX) Block Diagram
214
Dax Signals
214
Dax Functional Overview
215
Dax Programming Model
216
Dax Internal Architecture
216
Table 8-1 DAX Interrupt Vectors
216
Table 8-2 DAX Interrupt Priority
216
DAX Audio Data Registers a and B (XADRA/XADRB)
217
DAX Audio Data Buffer (XADBUF)
217
Figure 8-2 DAX Programming Mode
217
DAX Audio Data Shift Register (XADSR)
218
DAX Control Register (XCTR)
218
DAX Enable (XEN)-Bit 0
218
DAX Interrupt Enable (XIEN)-Bit 1
218
DAX Stop Control (XSTP)-Bit 2
218
DAX Clock Input Select (XCS[1:0])-Bits 3-4
219
XCTR Reserved Bits-Bits 5-9, 16-23
219
DAX Channel a Validity (XVA)-Bit 10
219
DAX Channel a User Data (XUA)-Bit 11
219
DAX Channel a Channel Status (XCA)-Bit 12
219
DAX Channel B Validity (XVB)-Bit 13
219
Table 8-3 Clock Source Selection
219
DAX Audio Data Register Empty (Xade)—Bit 0
220
DAX Channel B User Data (XUB)-Bit 14
220
DAX Channel B Channel Status (XCB)-Bit 15
220
DAX Status Register (XSTR)
220
XSTR Reserved Bits-Bits 1, 5-23
220
DAX Transmit Underrun Error Flag (XAUR)-Bit 2
220
Figure 8-3 DAX Relative Timing
221
DAX Block Transfer Flag (XBLK)-Bit 3
221
DAX Transmit in Progress (XTIP)-Bit 4
221
Table 8-4 Preamble Bit Patterns
222
DAX Non-Audio Data Buffer (XNADBUF)
222
DAX Parity Generator (PRTYG)
222
DAX Biphase Encoder
222
DAX Preamble Generator
222
Figure 8-4 Preamble Sequence
223
Figure 8-5 Clock Multiplexer Diagram
223
DAX Clock Multiplexer
223
DAX State Machine
224
Dax Programming Considerations
224
Initiating a Transmit Session
224
Transmit Register Empty Interrupt Handling
224
Block Transferred Interrupt Handling
224
DAX Operation During Stop
225
A.1 Introduction
228
A.2 Bootstrapping the Dsp
228
A.3 Bootstrap Program Listing
228
Introduction
228
Bootstrapping the Dsp
228
Bootstrap Program Listing
228
B.1 Introduction
234
B.2 Peripheral Addresses
234
B.3 Interrupt Addresses
234
B.4 Interrupt Priorities
234
B.5 Instruction Set Summary
234
B.6 Programming Sheets
234
Introduction
235
Peripheral Addresses
235
Interrupt Addresses
235
Interrupt Priorities
235
Instruction Set Summary
235
Programming Sheets
235
Figure B-1 On-Chip Peripheral Memory Map
236
Table B-1 Interrupt Starting Addresses and Sources
237
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