Motorola MC68EC020 Manuals

Manuals and User Guides for Motorola MC68EC020. We have 1 Motorola MC68EC020 manual available for free PDF download: User Manual

Motorola MC68EC020 User Manual

Motorola MC68EC020 User Manual (306 pages)

Brand: Motorola | Category: Computer Hardware | Size: 1.32 MB

Table of Contents

Introduction
2
- Table of Contents
  3
- SECTION 1: OVERVIEW um Rev
  16
Features
19
MC68020/EC020 Block Diagram
20
Programming Model
21
Supervisor Programming Model Supplement
23
Status Register (SR)
24
Data Types and Addressing Modes Overview
25
Instruction Set Overview
27
Virtual Memory and Virtual Machine Concepts
27
Virtual Memory
27
Virtual Machine
29
Pipelined Architecture
29
Cache Memory
30
Processing States

31
- Privilege Levels
  32
- Supervisor Privilege Level
  32
- User Privilege Level
  33
- Changing Privilege Level
  33
- Address Space Types
  34
- Exception Processing
  35
- Exception Vectors
  35
- Exception Stack Frame
  36
Signal Description

37
- Functional Signal Groups
  37
- Signal Index
  38
- Function Code Signals (FC2-FC0)
  38
- Address Bus (A31-A0, MC68020)(A23-A0, MC68EC020)
  38
- Data Bus (D31-D0)
  38
- Transfer Size Signals (SIZ1, SIZ0)
  38
- Signal Index
  39
- Asynchronous Bus Control Signals
  40
- Interrupt Control Signals
  41
- Bus Arbitration Control Signals
  42
- Bus Exception Control Signals
  42
- Emulator Support Signal
  43
- Clock (CLK)
  43
- Power Supply Connections
  43
- Signal Summary
  44
On-Chip Cache Memory

45
Bus Operation

49
Exception Processing

127
- Exception Processing Sequence
  127
- Exception Vector Assignments
  129
- Reset Exception
  130
- Bus Error Exception
  130
- Reset Operation Flowchart
  131
- Address Error Exception
  132
- Instruction Trap Exception
  132
- Illegal Instruction and Unimplemented Instruction Exceptions
  133
- Privilege Violation Exception
  134
- Trace Exception
  135
- Format Error Exception
  136
- Interrupt Exceptions
  137
- Interrupt Pending Procedure
  138
- Interrupt Recognition Examples
  140
- Assertion of IPEND (MC68020 Only)
  141
- Interrupt Exception Processing Flowchart
  142
- Breakpoint Instruction Exception
  144
- Multiple Exceptions
  144
- Breakpoint Instruction Flowchart
  145
- Return from Exception
  146
- RTE Instruction for Throwaway Four-Word Frame
  147
- Bus Fault Recovery
  148
- Special Status Word (SSW)
  148
- Special Status Word Format
  149
- Using Software to Complete the Bus Cycles
  150
- Completing the Bus Cycles with RTE
  151
- Coprocessor Considerations
  152
- Exception Stack Frame Formats
  152
  - Coprocessor Interface Description
    155
- Introduction
  155
  - Interface Features
    156
  - Concurrent Operation Support
    156
  - Coprocessor Instruction Format
    157
  - Coprocessor System Interface
    158
    
    Coprocessor Classification
    158
    
    Coprocessor Interface Register Selection
    159
    
    Processor-Coprocessor Interface
    159
- Coprocessor Instruction Types
  161
  - Coprocessor General Instructions
    162
    
    Branch on Coprocessor Condition Instruction
    166
    
    Set on Coprocessor Condition Instruction
    168
    
    Format
    170
    
    Protocol
    170
    
    Protocol
    171
  - Coprocessor Context Save and Restore Instructions
    171
    
    Coprocessor Internal State Frames
    172
    
    Coprocessor Format Words
    173
    
    Empty/Reset Format Word
    173
    
    Not-Ready Format Word
    174
    
    Valid Format Word
    175
    
    Coprocessor Context Restore Instruction
    177
- Coprocessor Interface Register Set
  179
- Response CIR
  179
- Control CIR
  179
- Save CIR
  180
- Restore CIR
  180
- Operation Word CIR
  180
- Command CIR
  180
- Condition CIR
  181
- Operand CIR
  181
- Register Select CIR
  182
- Instruction Address CIR
  182
- Operand Address CIR
  182
- Coprocessor Response Primitives
  182
- Scanpc
  183
- Coprocessor Response Primitive General Format
  183
- Busy Primitive
  185
- Null Primitive
  186
- Null Coprocessor Response Primitive Encodings
  187
- Supervisor Check Primitive
  188
- Transfer Operation Word Primitive
  188
- Transfer from Instruction Stream Primitive
  189
- Evaluate and Transfer Effective Address Primitive
  190
- Evaluate Effective Address and Transfer Data Primitive
  190
- Valid Effective Address Field Codes
  191
- Write to Previously Evaluated Effective Address Primitive
  192
- Take Address and Transfer Data Primitive
  194
- Transfer To/From Top of Stack Primitive
  195
- Transfer Single Main Processor Register Primitive
  195
- Transfer Main Processor Control Register Primitive
  196
- Transfer Multiple Main Processor Registers Primitive
  197
- Transfer Multiple Coprocessor Registers Primitive
  197
- Transfer Multiple Coprocessor Registers Primitive Format
  198
- Transfer Status Register and Scanpc Primitive
  199
- Take Preinstruction Exception Primitive
  200
- MC68020/EC020 Preinstruction Stack Frame
  201
- Take Midinstruction Exception Primitive
  202
- Take Postinstruction Exception Primitive
  203
- Coprocessor-Detected Exceptions
  204
- Main-Processor-Detected Exceptions
  207
  - Protocol Violations
    207
  - Exceptions Related to Primitive Processing
    208
  - F-Line Emulator Exceptions
    209
- Privilege Violations
  210
- Cptrapcc Instruction Traps
  210
- Trace Exceptions
  210
- Interrupts
  211
- Format Errors
  212
- Address and Bus Errors
  212
- Coprocessor Reset
  213
- Coprocessor Summary
  213
Instruction Execution Timing

216
- Timing Estimation Factors
  216
- Instruction Cache and Prefetch
  216
- Operand Misalignment
  217
- Bus/Sequencer Concurrency
  217
- Instruction Execution Overlap
  218
- Instruction Stream Timing Examples
  219
- Processor Activity for Example 1
  220
- Processor Activity for Example 2
  221
- Processor Activity for Example 3
  222
- Processor Activity for Example 4
  223
- Instruction Timing Tables
  224
- Instruction Timings from Timing Tables
  226
- Fetch Effective Address
  228
- Fetch Immediate Effective Address
  229
- Calculate Effective Address
  231
- Calculate Immediate Effective Address
  232
- Jump Effective Address
  234
- MOVE Instruction
  235
- Special-Purpose MOVE Instruction
  244
- Arithmetic/Logical Instructions
  245
- Immediate Arithmetic/Logical Instructions
  246
- Binary-Coded Decimal Operations
  247
- Single-Operand Instructions
  248
- Shift/Rotate Instructions
  249
- Bit Manipulation Instructions
  250
- Bit Field Manipulation Instructions
  251
- Conditional Branch Instructions
  252
- Control Instructions
  253
- Exception-Related Instructions
  254
- Save and Restore Operations
  255
Applications Information

256
- Floating-Point Units
  256
- Bit Data Bus Coprocessor Connection
  257
- Chip Select Generation PAL
  258
- Chip Select PAL Equations
  259
- Byte Select Logic for the MC68020/EC020
  260
- Data Bus Activity for Byte, Word, and Long-Word Ports
  261
- Example MC68020/EC020 Byte Select PAL System Configuration
  262
- MC68020/EC020 Byte Select PAL Equations
  263
- Power and Ground Considerations
  264
- Clock Driver
  265
- Memory Interface
  266
- Access Time Calculations
  267
- Access Time Computation Diagram
  268
- Memory Access Time Equations at 16.67 and 25 Mhz
  269
- Module Support
  270
- Module Descriptor
  270
- Module Stack Frame
  272
- Access Levels
  273
- Access Level Control Bus Registers
  273
- Module Call
  274
- Module Return
  275
Electrical Characteristics

276
Ordering Information and Mechanical Data

289
Appendix A

300
Interfacing an MC68EC020 to a DMA Device that

300

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