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KS8910
Samsung KS8910 Ethernet Transceiver Manuals
Manuals and User Guides for Samsung KS8910 Ethernet Transceiver. We have
1
Samsung KS8910 Ethernet Transceiver manual available for free PDF download: User Manual
Samsung KS8910 User Manual (99 pages)
100/10 Mbps Ethernet Transceriver
Brand:
Samsung
| Category:
Transceiver
| Size: 0.85 MB
Table of Contents
Important Notice
2
Table of Contents
5
Introduction
10
Product Overview
10
Features
11
Ethernet 10Base-T and 100Base-TX Block Diagram
12
Reference Documents
13
External Signals
14
Overview
14
External Signals
15
Pin Assignments
16
Signal Descriptions
17
Functional Blocks
22
MII Data Interface
22
Auto-Negotiation
23
Control Registers / Status Registers
23
Management Agent
23
Power Management
23
Base-TX Digital Block
24
100Base-TX and 10Base-T Analog Blocks
26
100 Base-TX Digital Blocks
28
10Base-T Digital Block
26
Overview
28
Physical Coding Sublayer (PCS)
28
Physical Medium Attachment Sublayer (PMA)
29
Physical Medium Dependent Sublayer (PMD)
29
Description of Operation
29
Base-TX Operational Block Diagram of KS8910
30
Physical Coding Sublayer (PCS)
31
4B/5B Encoder, Decoder
31
B/5B Coding of KS8910
32
5B Encoder (Transmit STM)
33
5B Decoder(Receive STM)
33
B/5B Encoder (Transmit) State Diagram of KS8910
34
B/4B Decoder (Receive) State Diagram of KS8910
35
Parallel and Serial Converters
36
Carrier Sense
36
Physical Medium Attachment (PMA)
37
Scrambling
37
Descramble Function of KS8910
38
Link Monitor
39
NRZ to NRZI and NRZI to NRZ Conversion
40
Physical Medium Dependent Sublayer
41
10 Base-T Digital Blocks
42
Jabber Control Function
42
Overview
42
Transmit Function
42
State Diagram of Jabber Control Function
43
Receive Function
44
Polarity Reverse Function
44
Collision Detection Function
45
SQE Function
44
Link Integrity Test
46
Analog Blocks
48
Loopback Function
46
Overview
48
100Mbit/S Transmit Circuits
49
Frequency Synthesizer
50
Crystal Oscillator
50
Transmit Twisted-Pair Driver
51
100Mbit/S Receive Circuits
52
Receiver Buffer
52
Adaptive Equalizer
53
Base Line Restore
53
Clock Recovery
53
10Mbit/S Receive Circuits
54
Receiver
54
Registers
56
10Mbit/S Transmit Circuits
54
Transmit Wave Shaper
54
Overview
56
Register Definitions
57
Base Mode Control : Register 0
57
Base Mode Status : Register 1
60
PHY Identifier 1 : Register 2
61
PHY Identifier 2 : Register 3
61
Auto-Negotiation Advertisement : Register 4
62
Auto-Negotiation Link Partner Ability : Register 5
63
Auto-Negotiation Expansion : Register 6
64
Auto-Negotiation Next Page Transmit Register : Register 7
65
10Base-T Control Register : Register 16
66
100Base-TX Control Register : Register 17
67
PHY Address Register : Register 18
67
Map Table Register 0 : Register 19
68
Map Table Register 1 : Register 20
68
Analog Control Register 0 : Register 21
69
Analog Control Register 1 : Register 22
69
Analog Status Register : Register 23
70
10Base-T Status Register : Register 24
70
100Base-T Status Register : Register 25
71
Electrical Characteristics
72
Absolute Maximum Ratings
73
Recommended Operating Ranges
73
D.C Electrical Characteristics
74
MII PADS Specification
74
100Base-Tx Transceiver Specification
74
10Base-T Transceiver Characteristics
75
Timming
76
OSC Clock Frequency
76
MII-Transmit Clock Tolerance
76
MII-Receive Clock Tolerance
77
MII/10Base-T Transmit Timing
78
MII/10Base-T Receive Timing
79
MII/100Base-TX Transmit Timing
80
MII/100Base-TX Receive Timing
81
MII-Management Interface Timing
82
POWER on Reset Timming
83
10Base-T SQE(Heartbeat) Timing
84
10Base-T Jabber Timing
85
10Base-T Normal Link Pulse Timing
86
Auto- Negotiation and Fast Link Pulse Timing
87
NIC Applications
88
Mechanical Data
90
Package Dimension
90
Section 11 Appendix
92
Glossary
92
Ethernet and Networking Acronyms and Terms
92
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