Page 1 User’s Manual 78K/0 Series Instructions Common to 78K/0 Series Document No. U12326EJ4V0UM00 (4th edition) Date Published October 2001 N CP(K) © 1995 Printed in Japan...
Page 2 [MEMO] User's Manual U12326EJ4V0UM...
Page 3 I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. IEBus is a trademark of NEC Corporation. Caution: Purchase of NEC I C components conveys a license under the Philips I...
Page 4 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
Page 5 Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 6 Major Revisions in This Edition Page Description Throughout Deletion of all information except for information common to the 78K/0 Series (for individual product information, refer to the user’s manual of each product). The mark shows major revised points. User's Manual U12326EJ4V0UM...
Page 7 → Find the mnemonic in CHAPTER 4 INSTRUCTION SET and then check the • To learn about the various kinds of 78K/0 Series product instructions in general: → Read this manual in the order of CONTENTS. • To learn about the hardware functions of 78K/0 Series products: →...
Page 8 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. • Documents Common to 78K/0 Series User’s Manual Instructions Note Application Note Basic I Basic II Basic III Note Some subseries may not be covered.
Page 9: Table Of Contents
CHAPTER 1 MEMORY SPACE ... 12 1.1 Memory Spaces ...12 1.2 Internal Program Memory (Internal ROM) Space ... 12 1.3 Vector Table Area ... 12 1.4 CALLT Instruction Table Area ... 12 1.5 CALLF Instruction Entry Area ... 12 1.6 Internal Data Memory (Internal RAM) Space ... 12 1.7 Special Function Register (SFR) Area ...
Page 10 CHAPTER 5 EXPLANATION OF INSTRUCTIONS ... 46 5.1 8-Bit Data Transfer Instructions ... 48 5.2 16-Bit Data Transfer Instructions ... 51 5.3 8-Bit Operation Instructions ... 54 5.4 16-Bit Operation Instructions ... 63 5.5 Multiply/Divide Instructions ... 67 5.6 Increment/Decrement Instructions ... 70 5.7 Rotate Instructions ...75 5.8 BCD Adjust Instructions ...
Page 11 Figure No. Program Counter Configuration ... 14 Program Status Word Configuration ... 14 Stack Pointer Configuration ... 16 Data to Be Saved to Stack Memory ... 16 Data to Be Reset from Stack Memory ... 16 General-Purpose Register Configuration ... 18 Table No.
Page 12: Chapter 1 Memory Space
The internal high-speed RAM can also be used as a stack memory. (2) Buffer RAM There are some products in the 78K/0 Series to which buffer RAM is allocated. This RAM is used to store the transfer/receive data of serial interface channel 1 (3-wire serial I/O mode with automatic transfer/receive function).
Page 13: Special Function Register (Sfr) Area
(3) RAM for VFD display There are some products in the 78K/0 Series to which RAM for VFD display is allocated. This RAM can also be used as an ordinary RAM area. (4) Internal expansion RAM There are some products in the 78K/0 Series to which internal expansion RAM is allocated.
Page 14: Chapter 2 Registers
2.1 Control Registers The control registers control the program sequence, statuses and stack memory. A program counter, a program status word and a stack pointer are the control registers. 2.1.1 Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed. In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched.
Page 15 (1) Interrupt enable flag (IE) This flag controls the interrupt request acknowledgement operations of the CPU. When IE = 0, the IE flag is set to interrupt disable (DI), and interrupts other than non-maskable interrupts are all disabled. When IE = 1, the IE flag is set to interrupt enable (EI), and interrupt request acknowledgement is controlled by an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority specification flag.
Page 16: Stack Pointer (Sp)
2.1.3 Stack pointer (SP) This is a 16-bit register that holds the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 2-3. Stack Pointer Configuration The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory.
Page 17: General-Purpose Registers
2.2 General-Purpose Registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. These registers consist of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L and H). In addition that each register can be used as an 8-bit register, two 8-bit registers in pairs can be used as a 16- bit register (AX, BC, DE and HL).
Page 18: General-Purpose Register Configuration
Figure 2-6. General-Purpose Register Configuration FEFFH BANK0 FEF8H FEF7H BANK1 FEF0H FEEFH BANK2 FEE8H FEE7H BANK3 FEE0H FEFFH BANK0 FEF8H FEF7H BANK1 FEF0H FEEFH BANK2 FEE8H FEE7H BANK3 FEE0H CHAPTER 2 REGISTERS (a) Absolute names 16-bit processing (b) Functional names 16-bit processing User's Manual U12326EJ4V0UM 8-bit processing...
Page 19: Special Function Registers (Sfrs)
2.3 Special Function Registers (SFRs) Unlike a general-purpose register, each special-function register has a special function. Special function registers are allocated in the 256-byte area FF00H to FFFFH. Special function registers can be manipulated, like general-purpose registers, by operation, transfer and bit manipulation instructions.
Page 20: Chapter 3 Addressing
3.1 Instruction Address Addressing An instruction address is determined by program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by the following addressing (for details of each instruction, refer to CHAPTER 5 EXPLANATION OF INSTRUCTIONS).
Page 21: Immediate Addressing
3.1.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the “CALL !addr16” or “BR !addr16” or “CALLF !addr11” instruction is executed. The CALL !addr16 and BR !addr16 instructions can be branched to all memory spaces. The CALLF !addr11 instruction is branched to the area of 0800H to 0FFFH.
Page 22: Table Indirect Addressing
3.1.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by the lower-5-bit immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and branched.
Page 23: Register Addressing
3.1.4 Register addressing [Function] The register pair (AX) contents to be specified by an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the “BR AX” instruction is executed. [Illustration] CHAPTER 3 ADDRESSING User's Manual U12326EJ4V0UM...
Page 24: Operand Address Addressing
[Function] This addressing automatically specifies the address of the registers that function as an accumulator (A and AX) in the general-purpose register area. Of the 78K/0 Series instruction words, the following instructions employ implied addressing. Instruction MULU A register for multiplicand and AX register for product storage...
Page 25: Register Addressing
3.2.2 Register addressing [Function] Register addressing accesses a general-purpose register as an operand. The general-purpose register to be accessed is specified by the register bank selection flags (RBS0 and RBS1) and the register specification codes (Rn and RPn) in the instruction codes. Register addressing is carried out when an instruction with the following operand format is executed.
Page 26: Direct Addressing
3.2.3 Direct addressing [Function] Direct addressing directly addresses the memory indicated by the immediate data in the instruction word. [Operand format] Identifier addr16 Label or 16-bit immediate data [Description example] MOV A, !FE00H; When setting !addr16 to FE00H Instruction code [Illustration] OP code addr16 (lower)
Page 27: Short Direct Addressing
3.2.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte fixed space FE20H to FF1FH. An internal high-speed RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
Page 28: Special-Function Register (Sfr) Addressing
3.2.5 Special-function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing. [Operand format] Identifier Special function register name...
Page 29: Register Indirect Addressing
3.2.6 Register indirect addressing [Function] Register indirect addressing addresses memory with register pair contents specified as an operand. The register pair to be accessed is specified by the register bank selection flags (RBS0 and RBS1) and the register pair specification in instruction codes. [Operand format] Identifier —...
Page 30: Based Addressing
3.2.7 Based addressing [Function] 8-bit immediate data is added to the contents of the HL register pair as a base register and the sum is used to address the memory. The HL register pair to be accessed is in the register bank specified by the register bank select flag (RBS0 and RBS1).
Page 31: Stack Addressing
3.2.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and RETURN instructions are executed or the register is saved/reset upon generation of an interrupt request. Stack addressing enables addressing of the internal high-speed RAM area only.
Page 32: Chapter 4 Instruction Set
This chapter lists the instructions in the 78K/0 Series instruction set. The instructions are common to all 78K/0 Series products. 4.1 Operation For the operation list for each product, refer to the user’s manual of each product. 4.1.1 Operand identifiers and description methods Operands are described in the “Operand”...
Page 33: Description Of "Operation" Column
4.1.2 Description of “operation” column A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer PSW: Program status word Carry flag...
Page 34: Description Of Number Of Clocks
4.1.4 Description of number of clocks 1 instruction clock cycle is 1 CPU clock cycle (f 4.1.5 Instructions listed by addressing type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ CHAPTER 4 INSTRUCTION SET ) selected by the processor clock control register (PCC).
Page 35 2nd Operand #byte 1st Operand ADDC SUBC ADDC SUBC ADDC SUBC B, C saddr ADDC SUBC !addr16 [DE] [HL] [HL+byte] [HL+B] [HL+C] Note Except r = A. CHAPTER 4 INSTRUCTION SET Note saddr !addr16 [DE] ADDC ADDC SUBC SUBC User's Manual U12326EJ4V0UM [HL] [HL+byte] $addr16 None...
Page 36 (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW 2nd Operand #word 1st Operand ADDW SUBW CMPW MOVW MOVW sfrp MOVW MOVW saddrp MOVW MOVW !addr16 MOVW MOVW MOVW Note Only when rp = BC, DE or HL. (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR 2nd Operand...
Page 37 (4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ 2nd Operand 1st Operand Basic Instructions Compound Instructions (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP CHAPTER 4 INSTRUCTION SET !addr16 !addr11 CALL...
Page 38: Instruction Codes
4.2 Instruction Codes 4.2.1 Description of instruction code table Immediate data corresponding to bit Data: 8-bit immediate data corresponding to byte Low/High byte: 16-bit immediate data corresponding to word Saddr-offset: 16-bit address lower 8-bit offset data corresponding to saddr Sfr-offset: sfr 16-bit address lower 8-bit offset data Low/High addr: 16-bit immediate data corresponding to addr16 jdisp:...
Page 39: Instruction Code List
4.2.2 Instruction code list Instruction Mnemonic Operands Group 8-Bit Data r,#byte Transfer saddr,#byte sfr,#byte Note Note A,saddr saddr,A A,sfr sfr,A A,!addr16 !addr16,A PSW,#byte A,PSW PSW,A A,[DE] [DE],A A,[HL] [HL],A A,[HL+byte] [HL+byte],A A,[HL+B] [HL+B],A A,[HL+C] [HL+C],A Note A,saddr A,sfr A,!addr16 A,[DE] A,[HL] A,[HL+byte] A,[HL+B]...
Page 40 Instruction Mnemonic Operands Group 16-Bit Data MOVW rp,#word Transfer saddrp,#word sfrp,#word AX,saddrp saddrp,AX AX,sfrp sfrp,AX Note 1 AX,rp Note 1 rp,AX AX,!addr16 !addr16,AX Note 1 XCHW AX,rp 8-Bit A,#byte Operation saddr,#byte Note 2 A,saddr A,!addr16 A,[HL] A,[HL+byte] A,[HL+B] A,[HL+C] ADDC A,#byte saddr,#byte Note 2...
Page 41 Instruction Mnemonic Operands Group 8-Bit A,#byte Operation saddr,#byte Note A,saddr A,!addr16 A,[HL] A,[HL+byte] A,[HL+B] A,[HL+C] SUBC A,#byte saddr,#byte Note A,saddr A,!addr16 A,[HL] A,[HL+byte] A,[HL+B] A,[HL+C] A,#byte saddr,#byte Note A,saddr A,!addr16 A,[HL] A,[HL+byte] A,[HL+B] A,[HL+C] Note Except r = A. CHAPTER 4 INSTRUCTION SET Operation Code 0 0 0 1 1 1 0 1 Data...
Page 42 Instruction Mnemonic Operands Group 8-Bit A,#byte Operation saddr,#byte Note A,saddr A,!addr16 A,[HL] A,[HL+byte] A,[HL+B] A,[HL+C] A,#byte saddr,#byte Note A,saddr A,!addr16 A,[HL] A,[HL+byte] A,[HL+B] A,[HL+C] A,#byte saddr,#byte Note A,saddr A,!addr16 A,[HL] A,[HL+byte] A,[HL+B] A,[HL+C] Note Except r = A. CHAPTER 4 INSTRUCTION SET Operation Code 0 1 1 0 1 1 0 1 Data...
Page 43 Instruction Mnemonic Operands Group 16-Bit ADDW AX,#word Operation SUBW AX,#word CMPW AX,#word Multiply/ MULU divide DIVUW Increment/ decrement saddr saddr INCW DECW Rotate RORC ROLC ROR4 [HL] ROL4 [HL] ADJBA Adjust ADJBS MOV1 CY,saddr.bit Manipulation CY,sfr.bit CY,A.bit CY,PSW.bit CY,[HL].bit saddr.bit,CY sfr.bit,CY A.bit,CY PSW.bit,CY...
Page 44 Instruction Mnemonic Operands Group CY,saddr.bit Manipulation CY,sfr.bit CY,A.bit CY,PSW.bit CY,[HL].bit XOR1 CY,saddr.bit CY,sfr.bit CY,A.bit CY,PSW.bit CY,[HL].bit SET1 saddr.bit sfr.bit A.bit PSW.bit [HL].bit CLR1 saddr.bit sfr.bit A.bit PSW.bit [HL].bit SET1 CLR1 NOT1 Call Return CALL !addr16 CALLF !addr11 CALLT [addr5] RETB RETI Stack PUSH...
Page 45 Instruction Mnemonic Operands Group Unconditional !addr16 Branch $addr16 Conditional BC $addr16 Branch $addr16 $addr16 $addr16 saddr.bit,$addr16 1 B sfr.bit,$addr16 A.bit,$addr16 PSW.bit,$addr16 [HL].bit,$addr16 saddr.bit,$addr16 0 0 1 1 0 0 0 1 0 B sfr.bit,$addr16 A.bit,$addr16 PSW.bit,$addr16 [HL].bit,$addr16 BTCLR saddr.bit,$addr16 0 0 1 1 0 0 0 1 0 B sfr.bit,$addr16 A.bit,$addr16 PSW.bit,$addr16...
Page 46: Chapter 5 Explanation Of Instructions
CHAPTER 5 This chapter explains the instructions of 78K/0 Series products. Each instruction is described with a mnemonic, including description of multiple operands. The basic configuration of instruction description is shown on the next page. For the number of instruction bytes and the instruction codes, refer to the user’s manual of each product and CHAPTER 4 INSTRUCTION SET, respectively.
Page 47 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Mnemonic [Instruction format] MOV dst, src: Indicates the basic description format of the instruction. dst ← src: Indicates instruction operation using symbols. [Operation] [Operand] Indicates operands that can be specified by this instruction. Refer to 4.1 Operation for the description of each operand symbol.
Page 48: 8-Bit Data Transfer Instructions
CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.1 8-Bit Data Transfer Instructions The following instructions are 8-bit data transfer instructions. MOV ... 49 XCH ... 50 User's Manual U12326EJ4V0UM...
Page 49 CHAPTER 5 EXPLANATION OF INSTRUCTIONS [Instruction format] MOV dst, src dst ← src [Operation] [Operand] Mnemonic Operand(dst,src) r, #byte saddr, #byte sfr, #byte A, r r, A A, saddr saddr, A A, sfr sfr, A A, !addr16 !addr16, A PSW, #byte Note Except r = A [Flag] PSW, #byte and PSW,...
Page 50 CHAPTER 5 EXPLANATION OF INSTRUCTIONS [Instruction format] XCH dst, src dst ↔ src [Operation] [Operand] Mnemonic Operand(dst,src) A, r A, saddr A, sfr A, !addr16 A, [DE] Note Except r = A [Flag] [Description] • The 1st and 2nd operand contents are exchanged. [Description example] XCH A, FEBCH;...
Page 51: 16-Bit Data Transfer Instructions
CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.2 16-Bit Data Transfer Instructions The following instructions are 16-bit data transfer instructions. MOVW ... 52 XCHW ... 53 User's Manual U12326EJ4V0UM...
Page 52 CHAPTER 5 EXPLANATION OF INSTRUCTIONS MOVW [Instruction format] MOVW dst, src dst ← src [Operation] [Operand] Mnemonic Operand(dst,src) MOVW rp, #word saddrp, #word sfrp, #word AX, saddrp saddrp, AX AX, sfrp Note Only when rp = BC, DE or HL [Flag] [Description] •...
Page 53 CHAPTER 5 EXPLANATION OF INSTRUCTIONS XCHW [Instruction format] XCHW dst, src dst ↔ src [Operation] [Operand] Mnemonic Operand(dst,src) XCHW AX, rp Note Only when rp = BC, DE or HL [Flag] [Description] • The 1st and 2nd operand contents are exchanged. [Description example] XCHW AX, BC;...
Page 54: 8-Bit Operation Instructions
CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.3 8-Bit Operation Instructions The following are 8-bit operation instructions. ADD ... 55 ADDC ... 56 SUB ... 57 SUBC ... 58 AND ... 59 OR ... 60 XOR ... 61 CMP ... 62 User's Manual U12326EJ4V0UM...
Page 55 CHAPTER 5 EXPLANATION OF INSTRUCTIONS [Instruction format] ADD dst, src dst, CY ← dst + src [Operation] [Operand] Mnemonic Operand(dst,src) A, #byte saddr, #byte A, r r, A A, saddr Note Except r = A [Flag] × × × [Description] •...
Page 56 CHAPTER 5 EXPLANATION OF INSTRUCTIONS ADDC [Instruction format] ADDC dst, src dst, CY ← dst + src + CY [Operation] [Operand] Mnemonic Operand(dst,src) ADDC A, #byte saddr, #byte A, r r, A A, saddr Note Except r = A [Flag] ×...
Page 57 CHAPTER 5 EXPLANATION OF INSTRUCTIONS [Instruction format] SUB dst, src dst, CY ← dst – src [Operation] [Operand] Mnemonic Operand(dst,src) A, #byte saddr, #byte A, r r, A A, saddr Note Except r = A [Flag] × × × [Description] •...
Page 58 CHAPTER 5 EXPLANATION OF INSTRUCTIONS SUBC [Instruction format] SUBC dst, src dst, CY ← dst – src – CY [Operation] [Operand] Mnemonic Operand(dst,src) SUBC A, #byte saddr, #byte A, r r, A A, saddr Note Except r = A [Flag] ×...
Page 59 CHAPTER 5 EXPLANATION OF INSTRUCTIONS [Instruction format] AND dst, src dst ← dst ∧ src [Operation] [Operand] Mnemonic Operand(dst,src) A, #byte saddr, #byte A, r r, A A, saddr Note Except r = A [Flag] × [Description] • Bit-wise logical product is obtained from the destination operand (dst) specified by the 1st operand and the source operand (src) specified by the 2nd operand and the result is stored in the destination operand (dst).
Page 60 CHAPTER 5 EXPLANATION OF INSTRUCTIONS [Instruction format] OR dst, src dst ← dst ∨ src [Operation] [Operand] Mnemonic Operand(dst,src) A, #byte saddr, #byte A, r r, A A, saddr Note Except r = A [Flag] × [Description] • The bit-wise logical sum is obtained from the destination operand (dst) specified by the 1st operand and the source operand (src) specified by the 2nd operand and the result is stored in the destination operand (dst).
Page 61 CHAPTER 5 EXPLANATION OF INSTRUCTIONS [Instruction format] XOR dst, src dst ← dst ∨ src [Operation] [Operand] Mnemonic Operand(dst,src) A, #byte saddr, #byte A, r r, A A, saddr Note Except r = A [Flag] × [Description] • The bit-wise exclusive logical sum is obtained from the destination operand (dst) specified by the 1st operand and the source operand (src) specified by the 2nd operand and the result is stored in the destination operand (dst).
Page 62 CHAPTER 5 EXPLANATION OF INSTRUCTIONS [Instruction format] CMP dst, src [Operation] dst – src [Operand] Mnemonic Operand(dst,src) A, #byte saddr, #byte A, r r, A A, saddr Note Except r = A [Flag] × × × [Description] • The source operand (src) specified by the 2nd operand is subtracted from the destination operand (dst) specified by the 1st operand.
Page 63: 16-Bit Operation Instructions
CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.4 16-Bit Operation Instructions The following are 16-bit operation instructions. ADDW ... 64 SUBW ... 65 CMPW ... 66 User's Manual U12326EJ4V0UM...
Page 64 CHAPTER 5 EXPLANATION OF INSTRUCTIONS ADDW [Instruction format] ADDW dst, src dst, CY ← dst + src [Operation] [Operand] Mnemonic Operand(dst,src) ADDW AX, #word [Flag] × × × [Description] • The destination operand (dst) specified by the 1st operand is added to the source operand (src) specified by the 2nd operand and the result is stored in the destination operand (dst).
Page 65 CHAPTER 5 EXPLANATION OF INSTRUCTIONS SUBW [Instruction format] SUBW dst, src dst, CY ← dst – src [Operation] [Operand] Mnemonic Operand(dst,src) SUBW AX, #word [Flag] × × × [Description] • The source operand (src) specified by the 2nd operand is subtracted from the destination operand (dst) specified by the 1st operand and the result is stored in the destination operand (dst) and the CY flag.
Page 66 CHAPTER 5 EXPLANATION OF INSTRUCTIONS CMPW [Instruction format] CMPW dst, src [Operation] dst – src [Operand] Mnemonic Operand(dst,src) CMPW AX, #word [Flag] × × × [Description] • The source operand (src) specified by the 2nd operand is subtracted from the destination operand (dst) specified by the 1st operand.
Page 67: Multiply/Divide Instructions
CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.5 Multiply/Divide Instructions The following are multiply/divide instructions. MULU ... 68 DIVUW ... 69 User's Manual U12326EJ4V0UM...
Page 68 CHAPTER 5 EXPLANATION OF INSTRUCTIONS MULU [Instruction format] MULU src AX ← A × src [Operation] [Operand] Mnemonic Operand(src) MULU [Flag] [Description] • The A register contents and the source operand (src) data are multiplied as unsigned data and the result is stored in the AX register.
Page 69 CHAPTER 5 EXPLANATION OF INSTRUCTIONS DIVUW [Instruction format] DIVUW dst AX (quotient), dst (remainder) ← AX [Operation] [Operand] Mnemonic Operand(dst) DIVUW [Flag] [Description] • The AX register contents are divided by the destination operand (dst) contents and the quotient and the remainder are stored in the AX register and the destination operand (dst), respectively.
Page 70: Increment/Decrement Instructions
CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.6 Increment/Decrement Instructions The following are increment/decrement instructions. INC ... 71 DEC ... 72 INCW ... 73 DECW ... 74 User's Manual U12326EJ4V0UM...
Page 71 CHAPTER 5 EXPLANATION OF INSTRUCTIONS [Instruction format] INC dst dst ← dst + 1 [Operation] [Operand] Mnemonic Operand(dst) saddr [Flag] × × [Description] • The destination operand (dst) contents are incremented by only one. • If the increment result is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0). •...
Page 72 CHAPTER 5 EXPLANATION OF INSTRUCTIONS [Instruction format] DEC dst dst ← dst – 1 [Operation] [Operand] Mnemonic Operand(dst) saddr [Flag] × × [Description] • The destination operand (dst) contents are decremented by only one. • If the decrement result is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0). •...
Page 73 CHAPTER 5 EXPLANATION OF INSTRUCTIONS INCW [Instruction format] INCW dst dst ← dst + 1 [Operation] [Operand] Mnemonic Operand(dst) INCW [Flag] [Description] • The destination operand (dst) contents are incremented by only one. • Because this instruction is frequently used for increment of a register (pointer) used for addressing, the Z, AC and CY flag contents are not changed.
Page 74 CHAPTER 5 EXPLANATION OF INSTRUCTIONS DECW [Instruction format] DECW dst dst ← dst – 1 [Operation] [Operand] Mnemonic Operand (dst) DECW [Flag] [Description] • The destination operand (dst) contents are decremented by only one. • Because this instruction is frequently used for decrement of a register (pointer) used for addressing, the Z, AC and CY flag contents are not changed.
Page 75: Rotate Instructions
CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.7 Rotate Instructions The following are rotate instructions. ROR ... 76 ROL ... 77 RORC ... 78 ROLC ... 79 ROR4 ... 80 ROL4 ... 81 User's Manual U12326EJ4V0UM...
Page 76 CHAPTER 5 EXPLANATION OF INSTRUCTIONS [Instruction format] ROR dst, cnt [Operation] (CY, dst [Operand] Mnemonic Operand(dst,cnt) A, 1 [Flag] × [Description] • The destination operand (dst) contents specified by the 1st operand are rotated to the right just once. • The LSB (bit 0) contents are simultaneously rotated to MSB (bit 7) and transferred to the CY flag. [Description example] ROR A, 1;...
Page 77 CHAPTER 5 EXPLANATION OF INSTRUCTIONS [Instruction format] ROL dst, cnt [Operation] (CY, dst [Operand] Mnemonic Operand(dst,cnt) A, 1 [Flag] × [Description] • The destination operand (dst) contents specified by the 1st operand are rotated to the left just once. • The MSB (bit 7) contents are simultaneously rotated to LSB (bit 0) and transferred to the CY flag. [Description example] ROL A, 1;...
Page 78 CHAPTER 5 EXPLANATION OF INSTRUCTIONS RORC [Instruction format] RORC dst, cnt (CY ← dst [Operation] [Operand] Mnemonic Operand(dst,cnt) RORC A, 1 [Flag] × [Description] • The destination operand (dst) contents specified by the 1st operand are rotated just once to the right with carry.
Page 79 CHAPTER 5 EXPLANATION OF INSTRUCTIONS ROLC [Instruction format] ROLC dst, cnt (CY ← dst [Operation] [Operand] Mnemonic Operand(dst,cnt) ROLC A, 1 [Flag] × [Description] • The destination operand (dst) contents specified by the 1st operand are rotated just once to the left with carry.
Page 80 CHAPTER 5 EXPLANATION OF INSTRUCTIONS ROR4 [Instruction format] ROR4 dst ← (dst) [Operation] [Operand] Mnemonic Operand(dst) ROR4 [HL] Note Specify an area other than the SFR area as operand [HL]. [Flag] [Description] • The lower 4 bits of the A register and the 2-digit data (4-bit data) of the destination operand (dst) are rotated to the right.
Page 81 CHAPTER 5 EXPLANATION OF INSTRUCTIONS ROL4 [Instruction format] ROL4 dst ← (dst) [Operation] [Operand] Mnemonic Operand(dst) ROL4 [HL] Note Specify an area other than the SFR area as operand [HL]. [Flag] [Description] • The lower 4 bits of the A register and the 2-digit data (4-bit data) of the destination operand (dst) are rotated to the left.
Page 82: Bcd Adjust Instructions
CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.8 BCD Adjust Instructions The following are BCD adjust instructions. ADJBA ... 83 ADJBS ... 84 User's Manual U12326EJ4V0UM...
Page 83 CHAPTER 5 EXPLANATION OF INSTRUCTIONS ADJBA [Instruction format] ADJBA [Operation] Decimal Adjust Accumulator for Addition [Operand] None [Flag] × × × [Description] • The A register, CY flag and AC flag are decimally adjusted from their contents. This instruction carries out an operation having meaning only when the BCD (binary coded decimal) data is added and the addition result is stored in the A register (in all other cases, the instruction carries out an operation having no meaning).
Page 84 CHAPTER 5 EXPLANATION OF INSTRUCTIONS ADJBS [Instruction format] ADJBS [Operation] Decimal Adjust Accumulator for Subtraction [Operand] None [Flag] × × × [Description] • The A register, CY flag and AC flag are decimally adjusted from their contents. This instruction carries out an operation having meaning only when the BCD (binary coded decimal) data is subtracted and the subtraction result is stored in the A register (in all other cases, the instruction carries out an operation having no meaning).
Page 85: Bit Manipulation Instructions
CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.9 Bit Manipulation Instructions The following are bit manipulation instructions. MOV1 ... 86 AND1 ... 87 OR1 ... 88 XOR1 ... 89 SET1 ... 90 CLR1 ... 91 NOT1 ... 92 User's Manual U12326EJ4V0UM...
Page 86 CHAPTER 5 EXPLANATION OF INSTRUCTIONS MOV1 [Instruction format] MOV1 dst, src dst ← src [Operation] [Operand] Mnemonic Operand(dst,src) MOV1 CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit [Flag] dst = CY × [Description] • Bit data of the source operand (src) specified by the 2nd operand is transferred to the destination operand (dst) specified by the 1st operand.
Page 87 CHAPTER 5 EXPLANATION OF INSTRUCTIONS AND1 [Instruction format] AND1 dst, src dst ← dst ∧ src [Operation] [Operand] Mnemonic Operand(dst,src) AND1 CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit [Flag] × [Description] • Logical product of bit data of the destination operand (dst) specified by the 1st operand and the source operand (src) specified by the 2nd operand is obtained and the result is stored in the destination operand (dst).
Page 88 CHAPTER 5 EXPLANATION OF INSTRUCTIONS [Instruction format] OR1 dst, src dst ← dst ∨ src [Operation] [Operand] Mnemonic Operand(dst,src) CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit [Flag] × [Description] • The logical sum of bit data of the destination operand (dst) specified by the 1st operand and the source operand (src) specified by the 2nd operand is obtained and the result is stored in the destination operand (dst).
Page 89 CHAPTER 5 EXPLANATION OF INSTRUCTIONS XOR1 [Instruction format] XOR1 dst, src dst ← dst ∨ src [Operation] [Operand] Mnemonic Operand(dst,src) XOR1 CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit [Flag] × [Description] • The exclusive logical sum of bit data of the destination operand (dst) specified by the 1st operand and the source operand (src) specified by the 2nd operand is obtained and the result is stored in the destination operand (dst).
Page 90 CHAPTER 5 EXPLANATION OF INSTRUCTIONS SET1 [Instruction format] SET1 dst dst ←1 [Operation] [Operand] Mnemonic Operand(dst) SET1 saddr.bit sfr.bit A.bit PSW.bit [HL].bit [Flag] dst = PSW.bit × × × [Description] • The destination operand (dst) is set (1). • When the destination operand (dst) is CY or PSW.bit, only the corresponding flag is set (1). [Description example] SET1 FE55H.1;...
Page 91 CHAPTER 5 EXPLANATION OF INSTRUCTIONS CLR1 [Instruction format] CLR1 dst dst ← 0 [Operation] [Operand] Mnemonic Operand(dst) CLR1 saddr.bit sfr.bit A.bit PSW.bit [HL].bit [Flag] dst = PSW.bit × × × [Description] • The destination operand (dst) is cleared (0). • When the destination operand (dst) is CY or PSW.bit, only the corresponding flag is cleared (0). [Description example] CLR1 P3.7;...
Page 92 CHAPTER 5 EXPLANATION OF INSTRUCTIONS NOT1 [Instruction format] NOT1 dst dst ← dst [Operation] [Operand] Mnemonic Operand(dst) NOT1 [Flag] × [Description] • The CY flag is inverted. [Description example] NOT1 CY; The CY flag is inverted. User's Manual U12326EJ4V0UM Not Single Bit (Carry Flag) 1 Bit Data Logical Negation...
Page 93: Call Return Instructions
CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.10 Call Return Instructions The following are call return instructions. CALL ... 94 CALLF ... 95 CALLT ... 96 BRK ... 97 RET ... 98 RETI ... 99 RETB ... 100 User's Manual U12326EJ4V0UM...
Page 94 CHAPTER 5 EXPLANATION OF INSTRUCTIONS CALL [Instruction format] CALL target (SP–1) ← (PC+3) [Operation] (SP–2) ← (PC+3) ← SP–2, ← target [Operand] Mnemonic Operand(target) CALL !addr16 [Flag] [Description] • This is a subroutine call with a 16-bit absolute address or a register indirect address. •...
Page 95 CHAPTER 5 EXPLANATION OF INSTRUCTIONS CALLF [Instruction format] CALLF Target (SP–1) ← (PC+2) [Operation] (SP–2) ← (PC+2) ← SP–2, ← target [Operand] Mnemonic Operand(target) CALLF !addr11 [Flag] [Description] • This is a subroutine call which can only be branched to addresses 0800H to 0FFFH. •...
Page 96 CHAPTER 5 EXPLANATION OF INSTRUCTIONS CALLT [Instruction format] CALLT [addr5] (SP–1) ← (PC+1) [Operation] (SP–2) ← (PC+1) ← SP–2, ← (00000000, addr5+1) ← (00000000, addr5) [Operand] Mnemonic Operand([addr5]) CALLT [addr5] [Flag] [Description] • This is a subroutine call for call table reference. •...
Page 97 CHAPTER 5 EXPLANATION OF INSTRUCTIONS [Instruction format] (SP–1) ← PSW, [Operation] (SP–2) ← (PC+1) (SP–3) ← (PC+1) ← 0, ← SP–3, ← (3FH), ← (3EH) [Operand] None [Flag] [Description] • This is a software interrupt instruction. • PSW and the next instruction address (PC+1) are saved to the stack. After that, the IE flag is cleared (0) and the saved data is branched to the address indicated with the word data at the vector address (003EH).
Page 98 CHAPTER 5 EXPLANATION OF INSTRUCTIONS [Instruction format] ← (SP), [Operation] ← (SP+1), SP ← SP+2 [Operand] None [Flag] [Description] • This is a return instruction from the subroutine call made with the CALL, CALLF and CALLT instructions. • The word data saved to the stack returns to the PC, and the program returns from the subroutine. User's Manual U12326EJ4V0UM Return Return from Subroutine...
Page 99 CHAPTER 5 EXPLANATION OF INSTRUCTIONS RETI [Instruction format] RETI ← (SP), [Operation] ← (SP+1), PSW ← (SP+2), ← SP+3, NMIS ← 0 [Operand] None [Flag] [Description] • This is a return instruction from the vectored interrupt. • The data saved to the stack returns to the PC and the PSW, and the program returns from the interrupt service routine.
Page 100 CHAPTER 5 EXPLANATION OF INSTRUCTIONS RETB [Instruction format] RETB ← (SP), [Operation] ← (SP+1), PSW ← (SP+2), ← SP+3 [Operand] None [Flag] [Description] • This is a return instruction from the software interrupt generated with the BRK instruction. • The data saved in the stack returns to the PC and the PSW, and the program returns from the interrupt service routine.
Page 101: Stack Manipulation Instructions
CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.11 Stack Manipulation Instructions The following are stack manipulation instructions. PUSH ... 102 POP ... 103 MOVW SP, src ... 104 MOVW AX, SP ... 104 User's Manual U12326EJ4V0UM...
Page 102 CHAPTER 5 EXPLANATION OF INSTRUCTIONS PUSH [Instruction format] PUSH src [Operation] When src = rp (SP–1) ← src (SP–2) ← src ← SP–2 [Operand] Mnemonic Operand(src) PUSH [Flag] [Description] • The data of the register specified by the source operand (src) is saved to the stack. [Description example] PUSH AX;...
Page 103 CHAPTER 5 EXPLANATION OF INSTRUCTIONS [Instruction format] POP dst [Operation] When dst = rp ← (SP), ← (SP+1), SP ← SP+2 [Operand] Mnemonic Operand(dst) [Flag] dst =rp [Description] • Data is returned from the stack to the register specified by the destination operand (dst). •...
Page 104 CHAPTER 5 EXPLANATION OF INSTRUCTIONS MOVW SP, src MOVW AX, SP [Instruction format] MOVW dst, src dst ← src [Operation] [Operand] Mnemonic Operand(dst,src) MOVW SP, #word SP, AX AX, SP [Flag] [Description] • This is an instruction to manipulate the stack pointer contents. •...
Page 105: Unconditional Branch Instruction
CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.12 Unconditional Branch Instruction The unconditional branch instruction is shown below. BR ... 106 User's Manual U12326EJ4V0UM...
Page 106 CHAPTER 5 EXPLANATION OF INSTRUCTIONS [Instruction format] BR target PC ← target [Operation] [Operand] Mnemonic Operand(target) !addr16 $addr16 [Flag] [Description] • This is an instruction to branch unconditionally. • The word data of the target address operand (target) is transferred to PC and branched. [Description example] BR AX;...
Page 107: Conditional Branch Instructions
CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.13 Conditional Branch Instructions Conditional branch instructions are shown below. BC ... 108 BNC ... 109 BZ ... 110 BNZ ... 111 BT ... 112 BF ... 113 BTCLR ... 114 DBNZ ... 115 User's Manual U12326EJ4V0UM...
Page 108 CHAPTER 5 EXPLANATION OF INSTRUCTIONS [Instruction format] BC $addr16 PC ← PC+2+jdisp8 if CY = 1 [Operation] [Operand] Mnemonic Operand($addr16) $addr16 [Flag] [Description] • When CY = 1, data is branched to the address specified by the operand. When CY = 0, no processing is carried out and the subsequent instruction is executed. [Description example] BC $300H;...
Page 109 CHAPTER 5 EXPLANATION OF INSTRUCTIONS [Instruction format] BNC $addr16 PC ← PC+2+jdisp8 if CY = 0 [Operation] [Operand] Mnemonic Operand($addr16) $addr16 [Flag] [Description] • When CY = 0, data is branched to the address specified by the operand. When CY = 1, no processing is carried out and the subsequent instruction is executed. [Description example] BNC $300H;...
Page 110 CHAPTER 5 EXPLANATION OF INSTRUCTIONS [Instruction format] BZ $addr16 PC ← PC+2+jdisp8 if Z = 1 [Operation] [Operand] Mnemonic Operand($addr16) $addr16 [Flag] [Description] • When Z = 1, data is branched to the address specified by the operand. When Z = 0, no processing is carried out and the subsequent instruction is executed. [Description example] DEC B BZ $3C5H;...
Page 111 CHAPTER 5 EXPLANATION OF INSTRUCTIONS [Instruction format] BNZ $addr16 PC ← PC+2+jdisp8 if Z = 0 [Operation] [Operand] Mnemonic Operand($addr16) $addr16 [Flag] [Description] • When Z = 0, data is branched to the address specified by the operand. When Z = 1, no processing is carried out and the subsequent instruction is executed. [Description example] CMP A, #55H BNZ $0A39H;...
Page 112 CHAPTER 5 EXPLANATION OF INSTRUCTIONS [Instruction format] BT bit, $addr16 PC ← PC+b+jdisp8 if bit = 1 [Operation] [Operand] Mnemonic Operand(bit,$addr16) saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 [Flag] [Description] • If the 1st operand (bit) contents have been set (1), data is branched to the address specified by the 2nd operand ($addr16).
Page 113 CHAPTER 5 EXPLANATION OF INSTRUCTIONS [Instruction format] BF bit, $addr16 PC ← PC+b+jdisp8 if bit = 0 [Operation] [Operand] Mnemonic Operand(bit,$addr16) saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 [Flag] [Description] • If the 1st operand (bit) contents have been cleared (0), data is branched to the address specified by the 2nd operand ($addr16).
Page 114 CHAPTER 5 EXPLANATION OF INSTRUCTIONS BTCLR [Instruction format] BTCLR bit, $addr16 PC ← PC+b+jdisp8 if bit = 1, then bit ← 0 [Operation] [Operand] Mnemonic Operand(bit,$addr16) BTCLR saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 [Flag] bit =PSW.bit ×...
Page 115 CHAPTER 5 EXPLANATION OF INSTRUCTIONS DBNZ [Instruction format] DBNZ dst, $addr16 dst ← dst–1, [Operation] then PC ← PC+b+jdisp16 if dst R1 [Operand] Mnemonic Operand(dst,$addr16) DBNZ B, $addr16 C, $addr16 saddr, $addr16 [Flag] [Description] • One is subtracted from the destination operand (dst) contents specified by the 1st operand and the subtraction result is stored in the destination operand (dst).
Page 116: Cpu Control Instructions
CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.14 CPU Control Instructions The following are CPU control instructions. SEL RBn ... 117 NOP ... 118 EI ... 119 DI ... 120 HALT ... 121 STOP ... 122 User's Manual U12326EJ4V0UM...
Page 117 CHAPTER 5 EXPLANATION OF INSTRUCTIONS SEL RBn [Instruction format] SEL RBn RBS0, RBS1 ← n; (n = 0-3) [Operation] [Operand] Mnemonic Operand(RBn) [Flag] [Description] • The register bank specified by the operand (RBn) is made a register bank for use by the next and subsequent instructions.
Page 118 CHAPTER 5 EXPLANATION OF INSTRUCTIONS [Instruction format] [Operation] no operation [Operand] None [Flag] [Description] • Only the time is consumed without processing. User's Manual U12326EJ4V0UM No Operation No Operation...
Page 119 CHAPTER 5 EXPLANATION OF INSTRUCTIONS [Instruction format] IE ← 1 [Operation] [Operand] None [Flag] [Description] • The maskable interrupt acknowledgeable status is set (by setting the interrupt enable flag (IE) to (1)). • No interrupts are acknowledged between this instruction and the next instruction. •...
Page 120 CHAPTER 5 EXPLANATION OF INSTRUCTIONS [Instruction format] IE ← 0 [Operation] [Operand] None [Flag] [Description] • Maskable interrupt acknowledgment by vectored interrupt is disabled (with the interrupt enable flag (IE) cleared (0)). • No interrupts are acknowledged between this instruction and the next instruction. •...
Page 121 CHAPTER 5 EXPLANATION OF INSTRUCTIONS HALT [Instruction format] HALT [Operation] Set HALT Mode [Operand] None [Flag] [Description] • This instruction is used to set the HALT mode to stop the CPU operation clock. The total power consumption of the system can be decreased with intermittent operation by combining this mode with the normal operation mode.
Page 122 CHAPTER 5 EXPLANATION OF INSTRUCTIONS STOP [Instruction format] STOP [Operation] Set STOP Mode [Operand] None [Flag] [Description] • This instruction is used to set the STOP mode to stop the main system clock oscillator and to stop the whole system. Power consumption can be minimized to only leakage current. User's Manual U12326EJ4V0UM Stop Stop Mode Set...
Page 123: Appendix Arevision History
Addition of the table of all internal RAM spaces of each model Change of the format of external memory space table Deletion of all information except for information common to the 78K/0 Series (for individual product information, refer to the user’s manual of each product). REVISION HISTORY...
Page 124: Appendix B Instruction Index (Mnemonic: By Function)
APPENDIX B INSTRUCTION INDEX (MNEMONIC: BY FUNCTION) [8-bit data transfer instructions] MOV ... 49 XCH ... 50 [16-bit data transfer instructions] MOVW ... 52 XCHW ... 53 [8-bit operation instructions] ADD ... 55 ADDC ... 56 SUB ... 57 SUBC ... 58 AND ...
Page 125 APPENDIX B INSTRUCTION INDEX (MNEMONIC: BY FUNCTION) [Unconditional branch instruction] BR ... 106 [Conditional branch instructions] BC ... 108 BNC ... 109 BZ ... 110 BNZ ... 111 BT ... 112 BF ... 113 BTCLR ...114 DBNZ ... 115 [CPU control instructions] SEL RBn ...
Page 126: Appendix Cinstruction Index (Mnemonic: In Alphabetical Order)
APPENDIX C INSTRUCTION INDEX (MNEMONIC: IN ALPHABETICAL ORDER) ADD ... 55 ADDC ... 56 ADDW ... 64 ADJBA ... 83 ADJBS ... 84 AND ... 59 AND1 ... 87 BC ... 108 BF ... 113 BNC ... 109 BNZ ... 111 BR ...
Page 127 APPENDIX C INSTRUCTION INDEX (MNEMONIC: IN ALPHABETICAL ORDER) SEL RBn ... 117 SET1 ... 90 STOP ... 122 SUB ... 57 SUBC ... 58 SUBW ... 65 XCH ... 50 XCHW ... 53 XOR ... 61 XOR1 ... 89 User's Manual U12326EJ4V0UM...
Page 128 [MEMO] User's Manual U12326EJ4V0UM...
Page 129 Taiwan NEC Electronics Taiwan Ltd. Fax: +886-2-2719-5951 Good Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. Despite all the care and precautions we've taken, you may encounter problems in the documentation.

NEC 78K/0 Series User Manual

Chapter 1 Memory Space

Chapter 2 Registers

Chapter 3 Addressing

Chapter 4 Instruction Set

Chapter 5 Explanation of Instructions

Appendix Arevision History

Appendix B Instruction Index (Mnemonic: by Function)

Appendix Cinstruction Index (Mnemonic: in Alphabetical Order)

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Summary of Contents for NEC 78K/0 Series

Table of Contents