Related Manuals for NEC mPD98409
Summary of Contents for NEC mPD98409
- Page 1 Information µ µ µ µ PD98409 Q&A (NEASCOT-S40C ATM LIGHT SAR CONTROLLER Document No. S14769EJ1V0IFJ1 (1st edition) Date Published December 2000 N CP(K) © 2000 Printed in Japan...
- Page 2 [MEMO] Information S14769EJ1V0IF00...
- Page 3 NOTES FOR CMOS DEVICES PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred.
- Page 4 NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others.
- Page 5 INTRODUCTION Target Readers This manual is intended for engineers who wish to understand the functions of the µ PD98409 and use it when designing application systems. Purpose This manual aims to answer questions asked by users of this product and has been prepared as a reference in cases where there are points that users feel require clarification.
- Page 6 [MEMO] Information S14769EJ1V0IF00...
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Page 7: Table Of Contents
CONTENTS CHAPTER 1 PINS ............................ 11 ................... Q.1.1 How does the RSTOUT_B pin operate? CHAPTER 2 PCI INTERFACE........................ 12 ..........Q.2.1 How should the Cache line size of the PCI configuration register be set? Which PCI commands are issued by the µ PD98409 when it is the master? .......... - Page 8 CHAPTER 6 TRANSMISSION SCHEDULER ..................20 Q.6.1 What is the relationship between the scheduler register settings (I, M, and P parameters) and ......................the actual transmission rate? Q.6.2 Is the same cell scheduling operation performed with scheduler register settings of I/M = 1/10 and ..........................
- Page 9 Q.8.9 Pools 0 to 7 are allocated as the receive pools for Raw cells. Can all the pools from 0 to 7 ....... be used for receiving Raw cells, or can only one of the pools from 0 to 7 be used? Q.8.10 What is the Alert level of a receive pool descriptor? Are the settings and interrupts of the Alert level ........................
- Page 10 CHAPTER 14 AC/DC CHARACTERISTICS................... 40 Q.14.1 When +5 V is supplied to the V pin, how much is the current consumption of the power supply? ..40 Q.14.2 Can a 5 V device be directly connected to the UTOPIA interface? ..........
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Page 11: Chapter 1 Pins
CHAPTER 1 PINS Q.1.1 How does the RSTOUT_B pin operate? A.1.1 The RSTOUT_B pin goes low at the same time as the RST_B pin and holds the low level for 11 to 22 clocks (BUSCLK input) after the RST_B pin has gone high. Reference: µ... -
Page 12: Chapter 2 Pci Interface
CHAPTER 2 PCI INTERFACE Q.2.1 How should the Cache line size of the PCI configuration register be set? A.2.1 The Cache line size setting is not related to the burst size when the µ PD98409 performs transfer as the master. The burst size is determined by the settings of the AD, TBE, and SZ fields in the GMR register. -
Page 13: What Is The Function Of The Retry Timer In The Pci Configuration Register
CHAPTER 2 PCI INTERFACE Q.2.4 What is the function of the Retry timer in the PCI configuration register? A.2.4 The µ PD98409 counts Retry, Disconnect, and Latency timeouts as the Retry timer count. If the number of all of these transfer interruptions exceeds the Retry timer count value, the FERR bit of the GSR register is set and operation is stopped. -
Page 14: Can Big Endian Format Be Used In Pci Bus Mode
CHAPTER 2 PCI INTERFACE Q.2.8 Can big endian format be used in PCI bus mode? A.2.8 No. Only little endian format is supported by the µ PD98409. Reference: µ PD98409 User’s Manual 4.1.1 Features of PCI bus interface Q.2.9 What is the value of the Revision ID in the PCI configuration register? Does this value change according to the version? A.2.9 The Revision ID is 02h, and is common to all versions. -
Page 15: How Long Does It Take For The Eeprom™ Connection Check And Automatic Loading
CHAPTER 2 PCI INTERFACE Q.2.12 How long does it take for the EEPROM™ connection check and automatic loading? A.2.12 The connection check takes about 600 clocks (BUSCLK input) and automatic loading about 2400 clocks (BUSCLK input). Reference: µ PD98409 User’s Manual 4.2 Serial EEPROM Interface Information S14769EJ1V0IF00... -
Page 16: Chapter 3 Utopia Interface
CHAPTER 3 UTOPIA INTERFACE Q.3.1 When should the TCLAV signal be deasserted? A.3.1 Deassert it between H2 (2 byte of the cell header) and P44 (44 byte of the payload). Do not deassert it at H1. T C L K T E N B L _ B T x C L A V P 4 6... -
Page 17: Can The Rclav Signal Be Deasserted In The Middle Of A Cell Transfer During Cell-Level Handshaking
CHAPTER 3 UTOPIA INTERFACE Q.3.4 Can the RCLAV signal be deasserted in the middle of a cell transfer during cell-level handshaking? A.3.4 Yes. The µ PD98409 does not fetch the data of Rx7 to Rx0 while the RCLAV signal is deasserted. When the RCLAV signal is asserted again, it starts fetching Rx7 to Rx0 as valid data. -
Page 18: Chapter 4 Control Memory
CHAPTER 4 CONTROL MEMORY Q.4.1 The µ PD98409 has an on-chip control memory, but is it possible to connect additional memories such as SRAM externally? A.4.1 SRAM cannot be additionally connected. The µ PD98409 supports 64 VCs (as the on-chip control memory) for transmission/reception. -
Page 19: Chapter 5 Mailbox
CHAPTER 5 MAILBOX Q.5.1 Can a mailbox be set straddling over the boundary of a 64 KB area? A.5.1 No, it cannot. A mailbox must fit into the area of 64 KB set by the MSH register (the higher 16 bits of the mailbox start address). -
Page 20: Chapter 6 Transmission Scheduler
CHAPTER 6 TRANSMISSION SCHEDULER Q.6.1 What is the relationship between the scheduler register settings (I, M, and P parameters) and the actual transmission rate? A.6.1 The scheduler register (I, M, and P parameters) is set in cell units. The average rate is set by I/M, which is the valid cell transmission of I cells per M cell. -
Page 21: Is It Possible To Control The Band Between Vcs
CHAPTER 6 TRANSMISSION SCHEDULER Q.6.4 Is it possible to control the band between VCs (for example, widen the cell transmission interval between VC1 and VC2)? A.6.4 Yes. Forcibly narrow the band by using an unassigned cell generator. If the priority of the unassigned cell generator is set to the highest level, all data cell intervals are extended by the band used for the unassigned cell generator. -
Page 22: What Is The Relationship Between Cell Transmission Scheduling And Dma Operations
CHAPTER 6 TRANSMISSION SCHEDULER Q.6.6 What is the relationship between cell transmission scheduling and DMA operations? A.6.6 The µ PD98409 determines the cell to be transmitted every 24 clocks by using the scheduler. After the cell to be transmitted has been determined, a DMA operation to read the cell data is executed. If the transmit FIFO has become full, the DMA operation to read cell data is stopped. -
Page 23: Chapter 7 Transmission
CHAPTER 7 TRANSMISSION Q.7.1 Is it possible for the transmit FIFO to overflow and for cells to be discarded? A.7.1 No. If the transmit FIFO has become full because the UTOPIA interface cannot transmit any more cells, cell data is not read. When the transmit FIFO has a vacancy, reading data is resumed. Reference: µ... -
Page 24: If A Transmit Queue Consists Of A Valid Packet Descriptor → Link Pointer → Blank Packet Descriptor
CHAPTER 7 TRANSMISSION Q.7.4 If a transmit queue consists of a valid packet descriptor → link pointer → blank packet descriptor sequence, to what does the Tx queue read pointer of the transmit VC table point on completion of transmission? A.7.4 The Tx queue read pointer points to the position of the link pointer. -
Page 25: When Are The Contents Of Packet Descriptor Word0 Stored In Transmit Vc Table Word0
CHAPTER 7 TRANSMISSION Q.7.6 When are the contents of packet descriptor Word0 stored in transmit VC table Word0? A.7.6 After the Tx_Ready command has been issued, the µ PD98409 reads the packet descriptor and stores the contents of packet descriptor Word0 in transmit VC table Word0, and then reads the data. Reference: µ... -
Page 26: Is There Any Problem If The Value Of The Vacant Field (Word1, Word2 Bits 31 To 16)
CHAPTER 7 TRANSMISSION Q.7.9 Is there any problem if the value of the vacant field (Word1, Word2 bits 31 to 16) of the transmit buffer descriptor is not 0? Are the values on the system memory rewritten? A.7.9 The vacant field (Word1, Word2 bits 31 to 16) may be a value other than 0. After reading two words of buffer descriptors, the µ... -
Page 27: How Can The Oam F5 Cell Be Transmitted
CHAPTER 7 TRANSMISSION Q.7.11 How can the OAM F5 cell be transmitted? A.7.11 It can be transmitted in the following two ways: (1) Open two transmit VCs and set the same VPI/VCI values to them. These VCs can be transmitted at the same time with one for an AAL-5 packet and the other for an OAM F5 cell. -
Page 28: Chapter 8 Reception
CHAPTER 8 RECEPTION Q.8.1 What will happen if a VPI/VCI value cell not enabled by the receive lookup table has been received, and is it reported? A.8.1 If a VPI/VCI value cell not enabled to be received is received, that cell is internally discarded. At this time, no notification, such as an interrupt, is made. -
Page 29: Is There A Limit To The Number Of Batches In The Receive Pool
CHAPTER 8 RECEPTION Q.8.3 Is there a limit to the number of batches in the receive pool? A.8.3 Yes. Up to 64K, equal to the number of bits in the Remaining number of batches field of a receive pool descriptor. Reference: µ... -
Page 30: How Should The T1 Time Register (T1R) Be Set To Detect A T1 Error
CHAPTER 8 RECEPTION Q.8.7 How should the T1 time register (T1R) be set to detect a T1 error? A.8.7 The setting of the T1R register should be the system clock time (BUSCLK input) × 64K. For example, where T1R = 5, the time required to detect a T1 error is 320K clocks (about 9.8 ms where BUSCLK = 33 MHz). Reference: µ... -
Page 31: What Kind Of Support Is There For Receive Vpi/Vci? When Reducing From Vpi/Vci 24 Bits To
CHAPTER 8 RECEPTION Q.8.11 What kind of support is there for receive VPI/VCI? When reducing from VPI/VCI 24 bits to VPI/VCI 15 bits via a setting in the VRR register, how is the area that is invalidated by SHIFT and MASK processed? A.8.11 Fields invalidated by SHIFT and MASK are ignored by the µ... -
Page 32: What Is The Packet Size Field In The Receive Indication
CHAPTER 8 RECEPTION Q.8.13 What is the Packet size field in the receive indication? A.8.13 The Packet size field indicates the size of a receive packet. The packet size can be specified to be in cell units or byte units. If an error occurs, however, the receive indication always reports the Packet size field in cell units. At this time, the packet size is the number of cells received and stored in the receive buffer up until the error occurs. -
Page 33: Chapter 9 Transmission/Reception
CHAPTER 9 TRANSMISSION/RECEPTION Q.9.1 Can the contents of the transmit/receive VC table be changed during transmission or reception? A.9.1 The contents of the VC table cannot be changed during transmission or reception, as changing these may cause the µ PD98409 to malfunction. Reference: µ... -
Page 34: To What Part Is The Crc-32 Operation Applied
CHAPTER 9 TRANSMISSION/RECEPTION Q.9.3 To what part is the CRC-32 operation applied? A.9.3 The CRC-32 operation is applied to the entire CPCS-PDU frame of User data, Padding, CPCS-UU, CPI, and Length. Reference: µ PD98409 User’s Manual 3.2 AAL-5 SAR Sublayer Function Q.9.4 Is the receive indication issued even when a Raw cell is received? A.9.4... -
Page 35: Chapter 10 Commands
CHAPTER 10 COMMANDS Q.10.1 What will happen if the Tx_Ready command is issued to a VC that is transmitting a packet (active VC)? A.10.1 The Tx_Ready command is ignored. However, Tx_Ready is acknowledged as a command, and the Busy bit of the CMR register is set for a specified time. -
Page 36: How Is The Nop Command Used
CHAPTER 10 COMMANDS Q.10.4 How is the NOP command used? A.10.4 The NOP command is issued two times to close a receive VC after the receive look-up table has been disabled, in the following sequence: (1) Disable the receive look-up table. (2) Issue the NOP command two times. -
Page 37: Chapter 11 Loopback
CHAPTER 11 LOOPBACK Q.11.1 Is valid data output to the PHY side (UTOPIA interface) in loopback mode? A.11.1 No. TENBL_B of the UTOPIA interface is deasserted (high level), invalidating the data. µ PD98409 Host UTOPIA Loopback Reference: µ PD98409 User’s Manual 5.8 Loopback Function Q.11.2 Does the pin status of the UTOPIA interface affect the transmit/receive operations of the µ... -
Page 38: Chapter 12 Registers
Reference: µ PD98409 User’s Manual 7.2 (1) GMR Q.12.4 What is the value of the VER register? A.12.4 K standard/E standard: VER = 0200h For the other versions, consult an NEC sales representative. Reference: µ PD98409 User’s Manual 7.2 (7) VER Information S14769EJ1V0IF00... -
Page 39: Chapter 13 Jtag
CHAPTER 13 JTAG Q.13.1 How can the JTAG function be reset when JTAG is not used? A.13.1 JTAG can be reset by two methods: one in which the JRST_B pin is used and one in which the JRST_B pin is not used. - Page 40 CHAPTER 14 AC/DC CHARACTERISTICS Q.14.1 When +5 V is supplied to the V pin, how much is the current consumption of the power supply? A.14.1 The +5 V power supply is used only to supply withstand voltage of 5 V to the PCI bus interface and does not affect the internal operation.
- Page 41 CHAPTER 15 OTHER ITEMS Q.15.1 Access is prohibited for 20 clocks (BUSCLK input) after reset. Does this mean that access is prohibited only after a hardware reset? A.15.1 Access is prohibited for 20 clocks after both hardware and software resets. Reference: µ...
- Page 42 [MEMO] Information S14769EJ1V0IF00...
- Page 43 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.