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Manuals and User Guides for NEC mPD98409. We have
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NEC mPD98409 manual available for free PDF download: Q&A
NEC mPD98409 Q&A (43 pages)
NEASCOT-S40C ATM LIGHT SAR CONTROLLER
Brand:
NEC
| Category:
Controller
| Size: 0.23 MB
Table of Contents
Table of Contents
7
Chapter 1 Pins
11
How Does the RSTOUT_B Pin Operate
11
Chapter 2 Pci Interface
12
How Should the Cache Line Size of the PCI Configuration Register be Set
12
Which PCI Commands Are Issued by the Μ PD98409 When It Is the Master
12
How Should the Latency Timer of the PCI Configuration Register be Set
12
What Is the Function of the Retry Timer in the PCI Configuration Register
13
When the Μ PD98409 Is the Target, What Happens if an Invalid Command Is Received
13
Are the Registers of the Μ PD98409 Mapped to the I/O Space or the Memory Space
13
Does the Μ PD98409 Support the Master Operation of AD Line Driving, Known as Arbitration Parking
13
If It Is Selected by the Arbiter When There Is no Master to Request Transfer on the PCI Bus
13
Can Big Endian Format be Used in PCI Bus Mode
14
What Is the Value of the Revision ID in the PCI Configuration Register? Does this Value Change According to the Version
14
Why Is It Impossible to Write 0 to Status Bits 31 to 27 and 24 in the PCI Configuration Register
14
What Are the Settings Related to Burst Size When the Μ PD98409 Performs a Transfer as the Master
14
How Long Does It Take for the EEPROM™ Connection Check and Automatic Loading
15
Chapter 3 Utopia Interface
16
When Should the TCLAV Signal be Deasserted
16
What Is the Phase Difference (Delay) between TCLK and RCLK
16
The Clocks of UTOPIA (TCLK and RCLK) Output the BUSCLK as Is. Can any Other Clocks be Used
16
Can the RCLAV Signal be Deasserted in the Middle of a Cell Transfer During Cell-Level Handshaking
17
Does the RENBL_B Signal Perform the same Operation in no Drop Mode (DR in GMR Register = 1) as in Octet or Cell-Level Handshake Mode
17
What Is the Status of the Tx7 to Tx0 Pins While the TENBL_B Signal Is Inactive (High Level)
17
An External PHY Device Is Connected to the UTOPIA Interface, but Controlled by an External Interface
17
At this Time, Is It Necessary to Use the PHY Control Interface of the Μ PD98409
17
Chapter 4 Control Memory
18
The Μ PD98409 Has an On-Chip Control Memory, but Is It Possible to Connect Additional Memories such as SRAM Externally
18
How Long Does It Take for the Control Memory to be Automatically Initialized after Reset
18
Are the Contents of the Control Memory Cleared to 0 When the Control Memory Is Automatically Initialized after Reset
18
Chapter 5 Mailbox
19
Can a Mailbox be Set Straddling over the Boundary of a 64 KB Area
19
When Does the Mailbox Become Full and How Is Transmission/Reception Stopped
19
Chapter 6 Transmission Scheduler
20
What Is the Relationship between the Scheduler Register Settings (I, M, and P Parameters) and the Actual Transmission Rate
20
Is the same Cell Scheduling Operation Performed with Scheduler Register Settings of I/M = 1/10 and I/M = 10/100
20
Is It Possible to Make the Priorities of Two or more Shapers the same
20
Is It Possible to Control the Band between Vcs
21
What Is the Time Set for Transmitting One Cell in Cell Transmission Scheduling
21
What Is the Relationship between Cell Transmission Scheduling and DMA Operations
22
Does the Host CPU Have to Set the a Bit of the Scheduler Register
22
Chapter 7 Transmission
23
Is It Possible for the Transmit FIFO to Overflow and for Cells to be Discarded
23
Is There a Limit to the Size of the Transmit Queue of each VC Configured with a Transmit Packet Descriptor
23
How Is Transmission Performed if SIZE = 0 Is Set for an AAL-5 Transmit Packet Descriptor
23
If a Transmit Queue Consists of a Valid Packet Descriptor → Link Pointer → Blank Packet Descriptor
24
Transmission
24
Can a Packet be Added During Transmission When the Transmit VC Is Active
24
When Are the Contents of Packet Descriptor Word0 Stored in Transmit VC Table Word0
25
Is There a Limit to the Number of Vcs Linked to a Shaper
25
Is There any Problem if the Value of the Vacant Field (Word1, Word2 Bits 31 to 16)
25
Of the Transmit Packet Descriptor Is Not 0? Are the Values on the System Memory Rewritten
25
Is There any Problem if the Value of the Vacant Field (Word1, Word2 Bits 31 to 16)
26
Of the Transmit Buffer Descriptor Is Not 0? Are the Values on the System Memory Rewritten
26
What Does the Packet Queue Pointer Field for Transmission Indication Indicate
26
How Can the OAM F5 Cell be Transmitted
27
Chapter 8 Reception
28
What will Happen if a VPI/VCI Value Cell Not Enabled by the Receive Lookup Table Has Been Received, and Is It Reported
28
How Is a CRC-10 Error Reported When a Raw Cell Is Received? Is It Possible to Disable Error Checking
28
Is There a Limit to the Number of Batches in the Receive Pool
29
Is It Possible to Temporarily Stop Reception for each VC
29
Are There Cases in Which a Receive Batch Is Consumed Even if a Receive Indication that Includes Error Information Has Been Reported
29
Is Only the User Data of AAL-5 CPCS-PDU Stored in the Receive Buffer When an AAL-5 Packet Is Received
29
How Should the T1 Time Register (T1R) be Set to Detect a T1 Error
30
Can the Receive Pool for Raw Cells be Shared with the Receive Pool for AAL-5
30
Pools 0 to 7 Are Allocated as the Receive Pools for Raw Cells. Can All the Pools from 0 to
30
Be Used for Receiving Raw Cells, or Can Only One of the Pools from 0 to 7 be Used
30
What Is the Alert Level of a Receive Pool Descriptor? Are the Settings and Interrupts of the Alert Level Valid for a Raw Cell Pool
30
What Kind of Support Is There for Receive VPI/VCI? When Reducing from VPI/VCI 24 Bits to
31
VPI/VCI 15 Bits Via a Setting in the VRR Register, How Is the Area that Is Invalidated by SHIFT and MASK Processed
31
How Should the UINFO Field of the Receive VC Table and Receive Indication be Used
31
What Is the Packet Size Field in the Receive Indication
32
Chapter 9 Transmission/Reception
33
Can the Contents of the Transmit/Receive VC Table be Changed During Transmission or Reception
33
How Many Bits Can be Supported for VPI/VCI
33
To What Part Is the CRC-32 Operation Applied
34
Is the Receive Indication Issued Even When a Raw Cell Is Received
34
Chapter 10 Commands
35
What will Happen if the Tx_Ready Command Is Issued to a VC that Is Transmitting a Packet
35
(Active VC)
35
What will Happen if the Close_Channel Command Is Issued with an Incorrect Setting for the Transmit or Receive VC Specified by the R/T Bit of the Command
35
When Accessing the Control Memory by Using the Indirect_Access Command, Can Two or more Addresses be Accessed by Issuing the Command Only Once
35
How Is the NOP Command Used
36
Chapter 11 Loopback
37
Is Valid Data Output to the PHY Side (UTOPIA Interface) in Loopback Mode
37
Does the Pin Status of the UTOPIA Interface Affect the Transmit/Receive Operations of the Μ PD98409 in Loopback Mode
37
Chapter 12 Registers
38
What Is the Function of the ADDR Register
38
How Are the ECCR and ERDR Registers Initialized
38
Can Transmission/Reception be Temporarily Halted by Clearing the SE and RE Bits of the GMR Register During Transmission/Reception
38
What Is the Value of the VER Register
38
Chapter 13 Jtag
39
How Can the JTAG Function be Reset When JTAG Is Not Used
39
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