User Manuals: Motorola DSP56367 Signal Processor

Manuals and User Guides for Motorola DSP56367 Signal Processor. We have 1 Motorola DSP56367 Signal Processor manual available for free PDF download: User Manual

Motorola DSP56367 User Manual

Motorola DSP56367 User Manual (524 pages)

24-Bit Digital Signal Processor

Brand: Motorola | Category: Processor | Size: 6.25 MB

Table of Contents

Table of Contents
3
Manual Conventions
29
DSP56367 Overview

31
- Introduction
  31
- DSP56300 Core Description
  32
- DSP56367 Audio Processor Architecture
  34
- DSP56300 Core Functional Blocks
  35
  - Data ALU
    35
    
    Data ALU Registers
    36
    
    Multiplier-Accumulator (MAC)
    36
  - Address Generation Unit (AGU)
    36
  - Program Control Unit (PCU)
    37
  - Internal Buses
    38
  - Direct Memory Access (DMA)
    39
  - PLL-Based Clock Oscillator
    39
  - JTAG TAP and Once Module
    40
  - On-Chip Memory
    40
  - Off-Chip Memory Expansion
    41
- Peripheral Overview
  41
Signal/Connection Descriptions

45
- Signal Groupings
  45
- Power
  48
- Ground
  48
- Clock and PLL
  49
- External Memory Expansion Port (Port A)
  50
  - External Address Bus
    50
  - External Data Bus
    50
  - External Bus Control
    50
- Interrupt and Mode Control
  52
- Parallel Host Interface (HDI08)
  53
- Serial Host Interface
  57
- Enhanced Serial Audio Interface
  59
- Enhanced Serial Audio Interface_1
  63
- SPDIF Transmitter Digital Audio Interface
  64
- Timer
  65
- Jtag/Once Interface
  65
  - Section 3 Specifications
    67
  - Thermal Characteristics
    68
  - DC Electrical Characteristics
    70
  - AC Electrical Characteristics
    71
  - Internal Clocks
    72
  - External Clock Operation
    73
  - Phase Lock Loop (PLL) Characteristics
    74
  - Reset, Stop, Mode Select, and Interrupt Timing
    75
    
    External Memory Expansion Port (Port A)
    83
    
    DRAM Timing
    88
    
    Arbitration Timings
    111
    
    Parallel Host Interface (HDI08) Timing
    112
    
    Serial Host Interface SPI Protocol Timing
    121
    
    Programming the Serial Clock
    129
    
    Enhanced Serial Audio Interface Timing
    132
- Digital Audio Transmitter Timing
  138
- Timer Timing
  139
- GPIO Timing
  140
- JTAG Timing
  141
  - Section 4 Design Considerations
    143
  - Electrical Design Considerations
    145
  - Power Consumption Considerations
    146
  - PLL Performance Issues
    147
    
    Section 5 Memory Configuration
    149
    
    Reserved Memory Spaces
    160
    
    External Memory Support
    161
Appendix B Equates

162
Appendix C JTAG BSDL

162
Appendix D Programmer's Reference

162
- Internal I/O Memory Map
  162
  - Section 6 Core Configuration
    167
  - Operating Mode Register (OMR)
    168
  - Address Tracing Enable (ATE) - Bit 15
    169
  - Operating Modes
    171
- Interrupt Priority Registers
  173
- DMA Request Sources
  179
- PLL Initialization
  180
- JTAG Identification (ID) Register
  181
  - Section 7 General Purpose Input/Output
    185
  - Port C Signals and Registers
    186
  - Section 8 Host Interface (HDI08)
    187
  - Interface - Host Side
    188
- HDI08 Host Port Signals
  190
- HDI08 Block Diagram
  191
- HDI08 – DSP-Side Programmer's Model
  192
- HDI08 – External Host Programmer's Model
  205
  - Interface Control Register (ICR)
    207
    
    ICR Double Host Request (HDRQ) Bit 2
    208
    
    ICR Host Flag 1 (HF1) Bit 4
    209
    
    ICR Initialize Bit (INIT) Bit 7
    210
  - Command Vector Register (CVR)
    211
    
    ISR Receive Data Register Full (RXDF) Bit 0
    212
    
    ISR Host Flag 3 (HF3) Bit 4
    213
  - Receive Byte Registers (RXH:RXM:RXL)
    214
  - Host Side Registers after Reset
    215
- Servicing the Host Interface
  216
  - Servicing Interrupts
    217
  - Section 9 Serial Host Interface
    219
Section 9 Serial Host Interface

220
Section 11 Enhanced Serial Audio Interface 1 (ESAI_1)

309
- ESAI_1 Data and Control Pins
  309
- DAX Signals
  326
- DAX Functional Overview
  327
- DAX Programming Model
  328
- DAX Internal Architecture
  329
  - DAX Audio Data Buffers (XADBUFA / XADBUFB)
    330
    
    DAX Channel a Channel Status (Xca)—Bit 12
    331
    
    Audio Data Register Empty Interrupt Enable (Xdie)—Bit 0
    332
    
    DAX Status Register (XSTR)
    333
    
    XSTR Reserved Bits—Bits 3–23
    334
    
    DAX Clock Multiplexer
    335
    
    DAX State Machine
    336
    
    Audio Data Register Empty Interrupt Handling
    337
    
    DAX Operation During Stop
    339
    
    Port D Control Register (PCRD)
    340
    
    Port D Data Register (PDRD)
    341
    
    Section 13 Timer/ Event Counter
    343
    
    Individual Timer Block Diagram
    344
- Timer/Event Counter Programming Model
  345
  - Prescaler Counter
    347
    
    TPLR Reserved Bit 23
    348
    
    Timer Control/Status Register (TCSR)
    349
    
    TCSR Inverter (INV) Bit 8
    351
    
    TCSR Timer Reload Mode (TRM) Bit 9
    352
    
    TCSR Data Input (DI) Bit 12
    353
    
    TCSR Timer Compare Flag (TCF) Bit 21
    354
  - Timer Compare Register (TCPR)
    355
- Timer Modes
  356
  - Timer Pulse (Mode 1)
    357
  - Timer Toggle (Mode 2)
    358
  - Timer Event Counter (Mode 3)
    359
  - Measurement Accuracy
    360
  - Measurement Input Period (Mode 5)
    361
  - Measurement Capture (Mode 6)
    362
  - Pulse Width Modulation (PWM, Mode 7)
    363
  - Watchdog Modes
    364
    
    Watchdog Toggle (Mode 10)
    365
  - Reserved Modes
    366
  - Section 14 Packaging
    367
  - LQFP Package Mechanical Drawing
    373
- Ordering Drawings
  374
  - A.1 DSP56367 Bootstrap Program
    375
  - D.1 Introduction
    433
  - D.2 Internal I/O Memory Map
    434
  - D.3 Interrupt Vector Addresses
    439
  - D.4 Interrupt Source Priorities (Within an IPL)
    442
  - D.5 Host Interface—Quick Reference
    444
  - D.6 Programming Sheets
    447
Appendix F IBIS Model

517
Appendix E Power Consumption Benchmark

517
Appendix F IBIS Model

517
- Index
  517

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